Overview
Unified CPU input format with TileLink protocols is a technique described in the DIFUZZRTL paper as part of the implementation of DIFUZZRTL, an RTL fuzzer for automatically discovering unknown bugs in CPU RTL designs.
The paper lists this technique among several methods added to address unique RTL design characteristics. In the abstract, it appears alongside:
- cycle-sensitive register coverage guiding,
- asynchronous interrupt events handling,
- a unified CPU input format with TileLink protocols, and
- drop-in-replacement designs.
Role in DIFUZZRTL
The available evidence supports identifying this technique as a named component of the DIFUZZRTL approach, rather than as a standalone protocol specification. Its purpose is not further detailed in the provided evidence, but it is explicitly presented as part of the engineering needed to make RTL fuzzing work for CPU designs.
Context from the paper
DIFUZZRTL was evaluated on three real-world open-source CPU RTLs:
- OpenRISC Mor1kx Cappuccino
- RISC-V Rocket Core
- RISC-V Boom Core
This establishes the technique as part of a practical fuzzing system evaluated on multiple CPU cores, though the provided evidence does not give deeper implementation details for the input format itself.