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Sequence Import/Export

Technique WIKI v1 · 5/27/2026

Sequence Import/Export is a testing technique for converting instruction traces to and from a human-readable format, enabling terminal reporting and trace-file workflows. In the cited TestRIG context, traces can be read and written individually or in bulk from a directory, which supports maintaining a regression-test library of previous counterexamples.

Overview

Sequence Import/Export is a technique for handling instruction traces in a human-readable representation. The cited TestRIG paper describes instruction traces as convertible both to and from this format, supporting use in terminal reporting as well as file-based trace workflows. [C1]

Trace-file workflow

The technique supports reading and writing trace files either one at a time or in bulk from a directory. This makes it suitable for workflows where generated or discovered traces need to be preserved, replayed, or organized as files. [C1]

Regression-test use

The cited authors state that this import/export capability enabled them to collect a library of regression tests for quickly checking previous counterexamples. They contrast these trace-based regression tests with hand-written tests with assertions, stating that the former do not require maintenance in the same way. [C2]

Role in sequence-based testing

The same source discusses related sequence-level mechanisms in the surrounding TestRIG/QCVEngine testing context, including smart shrinking, non-shrinkable sequences, and sequences that include assertions. These mechanisms are separate from import/export, but they show that imported or exported traces participate in a broader workflow for counterexample management and sequence-based CPU testing. [C3]

Implementations

The provided related-entity metadata identifies QCVEngine and TestRIG as tools that implement Sequence Import/Export.

LINKED ENTITIES

2 links
QCVEngine IMPLEMENTS
TestRIG IMPLEMENTS

CITATIONS

3 sources
3 citations
[1] Instruction traces can be converted to and from a human-readable format for terminal reporting and for reading and writing trace files, individually or in bulk from a directory. Randomized Testing of RISC-V CPUs using Direct
[2] Sequence Import/Export enabled collection of a regression-test library for quickly checking previous counterexamples, and the cited text contrasts these with hand-written tests with assertions as not requiring maintenance. Randomized Testing of RISC-V CPUs using Direct
[3] The surrounding sequence-based testing workflow includes smart shrinking, non-shrinkable sequences, and assertions in sequences. Randomized Testing of RISC-V CPUs using Direct