Skip to content
STIMSMITH

Memory Allocation Size Variation

Technique WIKI v1 · 9/21/2026

Memory allocation size variation is a source of edit-distance differences between ground-truth and predicted assembly code in CISC-to-RISC transpilation. Compilers and transpilers may emit different allocation sizes for the same logical data structure, provided the allocated memory remains sufficient for the program's needs.

Memory Allocation Size Variation

Definition

Memory allocation size variation is a phenomenon observed in assembly-level program representations (particularly in transpilation between instruction set architectures) in which two functionally equivalent code sequences allocate different amounts of memory for the same logical data structure or buffer. Despite the numerical difference, the allocation remains correct as long as the allocated region is sufficient for the program's needs.

Example (ARM/Thumb context)

In the context of ARM assembly, a documented instance of this variation is:

Direction Instruction
Ground truth mov r0, #400
Predicted mov r0, #800

Both sequences allocate a buffer (whose size is passed or stored in r0), but the predicted version allocates twice as much memory as the ground-truth version. The edit distance reported for this divergence is 23 — the largest among the simple single-axis variations catalogued for that program.

Why It Occurs

Memory allocation size variation arises because:

  1. Compilers and transpilers have freedom in sizing buffers. As long as the chosen size satisfies the upper bound of any subsequent memory access, the program remains semantically correct.
  2. No canonical size exists at the assembly level. Different compilers, optimization levels, or transpilation strategies may pick conservative larger allocations or tighter minimal allocations without changing program behavior.
  3. It is independent of other source-level equivalences. Register renaming, stack-slot permutation, instruction combining, and symbol renaming are separate phenomena that may co-occur with allocation-size differences.

Relationship to Other Variation Types

In the taxonomy of divergences between ground-truth and predicted assembly produced by language-modeling-based transpilers, memory allocation size variation sits alongside, but is distinct from:

  • Register selection for temporaries (edit distance 16)
  • Stack-location permutation for local variables (edit distance 12)
  • Compiler-generated symbol renaming (edit distance 6)
  • Instruction combination (edit distance 12)
  • Stack-frame offset variation (edit distance 4)
  • Instruction-sequence divergence producing the same logical result (edit distance 52)
  • Direct constant vs. literal-pool loading (edit distance 50)

Allocation size variation is typically the highest-cost single-axis variation among the simpler categories, reflecting the fact that the differing operand is a numerical literal of potentially large magnitude.

Implications for Transpilation Testing

Because allocation size variation preserves functional correctness as long as the predicted allocation is sufficient, equivalence-testing frameworks for CISC-to-RISC transpilation must not rely solely on textual or opcode-level diffing. Instead, behavioral testing (executing the transpiled program against the original and comparing observable outputs) is required to tolerate such variations. This is one of the categories of divergences that motivates the use of testing-based guarantees rather than syntactic matching in transpilation pipelines.

LINKED ENTITIES

1 links

CITATIONS

4 sources
4 citations
[1] Memory allocation sizes can vary between ground-truth and predicted assembly as long as the allocation remains sufficient for the program's needs. Guaranteed Guess: A Language Modeling Approach for CISC-to-RISC Transpilation with Testing Guarantees
[2] A documented instance of memory allocation size variation is a ground-truth `mov r0, #400` versus a predicted `mov r0, #800`, with an associated edit distance of 23. Guaranteed Guess: A Language Modeling Approach for CISC-to-RISC Transpilation with Testing Guarantees
[3] Memory allocation size variation is presented as one category among several divergences (register selection, stack-location permutation, symbol renaming, instruction combining, stack-frame offset variation, instruction-sequence divergence, and constant loading style) catalogued between ground-truth and predicted assembly in CISC-to-RISC transpilation. Guaranteed Guess: A Language Modeling Approach for CISC-to-RISC Transpilation with Testing Guarantees
[4] Because allocation-size variation preserves functional correctness when sufficient memory is provided, equivalence testing for transpilation must rely on behavioral execution rather than syntactic matching. Guaranteed Guess: A Language Modeling Approach for CISC-to-RISC Transpilation with Testing Guarantees