Overview
Interruption and Exception Simulation is a technique for CPU RTL fuzzing that simulates realistic CPU interruption and exception handling during test execution. In the Instiller work, interruptions and exceptions are treated as common CPU execution events whose simulation can help cover corner cases in CPU verification. [C1]
Motivation
The evidence identifies interruption and exception handling as a realism and coverage challenge for CPU fuzzing. Prior fuzzing work had considered interruptions only in a relatively simple way: exceptions were not simulated, and multiple interruptions and exceptions with their priorities were not included. According to the Instiller paper, omitting these situations prevents fuzzing from simulating real-world CPU execution and from covering all CPU states. [C2]
Technique
The technique described in Instiller has three main elements:
- Exception inclusion: exceptions are added to CPU fuzzing, which the paper states had not been proposed in the referenced prior work. [C3]
- Multiple events: more than one interruption and exception can be integrated into a test scenario, with the goal of simulating real-world CPU execution more comprehensively. [C4]
- Priority handling: priorities among different interruptions and exceptions are considered, which the paper says can fuzz the CPU more thoroughly. [C5]
Together, these elements are presented as a way to better simulate real-world interruption and exception handling than prior approaches. [C6]
Use in Instiller
Instiller is the prototype fuzzer that uses this technique. The paper lists support for multiple interruptions and exceptions, including their priorities, as one of Instiller's contributions, and states that these mechanisms can simulate realistic interruption and exception handling well. [C7]
Reported evaluation context
The cited Instiller evaluation reports overall tool-level improvements, including a 29.4% coverage increase and 17.0% more mismatches found in the targets. These results are reported for Instiller as a whole rather than isolated solely to interruption and exception simulation. [C8]