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STIMSMITH

Coverage Collector

Technique WIKI v1 · 5/25/2026

Coverage Collector

Overview

The coverage collector is a verification component in the UVM testbench for a SystemVerilog implementation of a 5-stage pipelined MIPS processor. The processor project includes hazard-handling capability and a UVM-based verification environment containing a randomizing instruction generator, a monitor, and the coverage collector.[1]

Context in the Verification Environment

The coverage collector exists as part of the processor’s UVM verification testbench. In the described environment, the major verification components are:

  • Randomizing instruction generator — produces randomized instruction stimulus.
  • Monitor — observes processor behavior during simulation.
  • Coverage collector — records verification coverage information from the observed or generated activity.[1]

This places the coverage collector in the measurement portion of the verification flow: it is used to determine how thoroughly the testbench exercises the MIPS processor design.

Target Design

The design under verification is a 5-stage pipelined MIPS CPU implemented in SystemVerilog.[1] The processor supports hazard handling, meaning the verification environment must account for scenarios involving pipeline hazards as well as normal instruction execution.[1]

Role

Within this project, the coverage collector is responsible for supporting verification closure by collecting coverage data during UVM simulations. The available evidence identifies it as one of the main UVM testbench components but does not specify its internal implementation, such as its covergroups, sampled signals, bins, or coverage goals.[1]

Implementation Notes

The provided evidence confirms only the presence of a coverage collector in the UVM testbench. It does not describe:

  • specific coverage models,
  • instruction classes covered,
  • pipeline-stage coverage,
  • hazard-specific coverpoints,
  • cross-coverage definitions,
  • sampling strategy,
  • or coverage report format.

Therefore, any detailed implementation behavior should be verified directly from the repository source code before being treated as authoritative.

References

[1]: Repository description for the MIPS CPU project, stating that it is a 5-stage pipelined MIPS processor in SystemVerilog with hazard handling and a UVM verification testbench including a randomizing instruction generator, monitor, and coverage collector. Source: 0ba83467-72ea-4215-8031-32f44ee7c3ab.