Zacharias Takakis

Person WIKI v1 · 5/28/2026

Zacharias Takakis is documented as the author of the 2019 MSc thesis "UVM-based verification of RISC-V superscalar processors: A reinforcement learning approach" at Democritus University of Thrace. The thesis proposed reinforcement-learning-inspired methods for automating test application in UVM-based verification of a 2-way superscalar out-of-order RISC-V processor.

Zacharias Takakis

Overview

Zacharias Takakis is identified in the available evidence as the author of the MSc thesis "UVM-based verification of RISC-V superscalar processors: A reinforcement learning approach", dated May 22, 2019. The thesis was produced at the Democritus University of Thrace, Department of Electrical and Computer Engineering, in the BS Lab of Integrated Circuits, under the supervision of Assistant Professor Georgios Dimitrakopoulos.[1]

Thesis topic

Takakis's thesis addresses front-end functional verification for RISC-V superscalar processors, with an emphasis on improving functional coverage and reducing test application time in verification flows.[2]

The thesis proposes two automation techniques for test application:

A multi-armed bandit decision-making model that automatically suggests which constrained-random or directed test sequences should be applied to the design under test in order to cover more functional properties.[3]
A feedback-based mechanism that dynamically adjusts how much test application time is assigned to each constrained-random test sequence based on its observed quality, allocating more cycles to higher-quality sequences and replacing underperforming sequences.[4]

Verification target and technical scope

The experimental design discussed in the thesis is described as a 2-way superscalar out-of-order RISC-V processor. The table of contents indicates technical coverage of the processor's instruction fetch, instruction decode, register renaming, instruction issue, execution, and writeback stages, as well as application of multi-armed bandit techniques to an instruction fetch unit and to a full RISC-V processor verification flow.[5]

Significance of the work

According to the thesis abstract, automating test application can improve functional coverage, reduce verification effort, and shorten time to market in processor verification projects.[6]

References

[1] Zacharias Takakis, "UVM-based verification of RISC-V superscalar processors: A reinforcement learning approach," MSc thesis, Democritus University of Thrace, May 22, 2019.

LINKED ENTITIES

2 links

Democritus University of Thrace degree_institution

Georgios Dimitrakopoulos thesis_supervisor

CITATIONS

6 sources

6 citations

[1] Zacharias Takakis authored the MSc thesis titled "UVM-based verification of RISC-V superscalar processors: A reinforcement learning approach," dated May 22, 2019, at Democritus University of Thrace, Department of Electrical and Computer Engineering, BS Lab of Integrated Circuits, supervised by Assistant Professor Georgios Dimitrakopoulos. [PDF] UVM-based verification of RISC-V superscalar processors

[2] The thesis focuses on front-end functional verification, functional coverage, and reducing test application time. [PDF] UVM-based verification of RISC-V superscalar processors

[3] The thesis proposes using a multi-armed bandit decision-making model to select constrained-random or directed test sequences for improving functional coverage. [PDF] UVM-based verification of RISC-V superscalar processors

[4] The thesis proposes a feedback-based mechanism that dynamically adjusts test application time for constrained-random test sequences and replaces underperforming sequences. [PDF] UVM-based verification of RISC-V superscalar processors

[5] The experimental design discussed in the thesis is a 2-way superscalar out-of-order RISC-V processor, and the contents cover processor stages including instruction fetch, decode, register renaming, issue, execution, and writeback. [PDF] UVM-based verification of RISC-V superscalar processors

[6] The thesis states that automating test application improves functional coverage, minimizes verification effort, and shortens time to market. [PDF] UVM-based verification of RISC-V superscalar processors