Democritus University of Thrace

Organization

Democritus University of Thrace is evidenced here through a 2019 MSc thesis hosted in its repository. The thesis identifies the university with the Department of Electrical and Computer Engineering and the Lab of Integrated Circuits, and names Assistant Professor Georgios Dimitrakopoulos as supervisor.

First seen 5/28/2026

Last seen 5/28/2026

Evidence 1 chunks

Wiki v1

WIKI

Overview

Democritus University of Thrace appears in the provided evidence as the institution associated with a May 22, 2019 MSc thesis titled UVM-based verification of RISC-V superscalar processors: A reinforcement learning approach by Zacharias Takakis. The thesis front matter lists Democritus University of Thrace together with the Department of Electrical and Computer Engineering and the Lab of Integrated Circuits.

Documented academic context

READ FULL ARTICLE →

NEIGHBORHOOD

No graph connections found for this entity yet. It may appear in future ingestion runs.

explore full graph →

RELATIONSHIPS

1 connections

Georgios Dimitrakopoulos ← part of 95% 1e

Georgios Dimitrakopoulos is an Assistant Professor at Democritus University of Thrace.

LINKED ENTITIES

1 links

Georgios Dimitrakopoulos PART_OF Extracted graph relationship

CITATIONS

5 sources

5 citations — click to expand

[1] A 2019 MSc thesis titled 'UVM-based verification of RISC-V superscalar processors: A reinforcement learning approach' is associated with Democritus University of Thrace. [PDF] UVM-based verification of RISC-V superscalar processors

[2] The thesis front matter lists the Department of Electrical and Computer Engineering and the Lab of Integrated Circuits under Democritus University of Thrace. [PDF] UVM-based verification of RISC-V superscalar processors

[3] Assistant Professor Georgios Dimitrakopoulos is named as supervisor of the thesis. [PDF] UVM-based verification of RISC-V superscalar processors

[4] The thesis abstract describes multi-armed bandit test-sequence selection and a feedback-based mechanism for adjusting constrained-random test application time. [PDF] UVM-based verification of RISC-V superscalar processors

[5] The thesis abstract states that the techniques were evaluated on a 2-way superscalar out-of-order RISC-V processor. [PDF] UVM-based verification of RISC-V superscalar processors