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Democritus University of Thrace

Organization WIKI v1 · 5/28/2026

Democritus University of Thrace is evidenced here through a 2019 MSc thesis hosted in its repository. The thesis identifies the university with the Department of Electrical and Computer Engineering and the Lab of Integrated Circuits, and names Assistant Professor Georgios Dimitrakopoulos as supervisor.

Overview

Democritus University of Thrace appears in the provided evidence as the institution associated with a May 22, 2019 MSc thesis titled UVM-based verification of RISC-V superscalar processors: A reinforcement learning approach by Zacharias Takakis. The thesis front matter lists Democritus University of Thrace together with the Department of Electrical and Computer Engineering and the Lab of Integrated Circuits.

Documented academic context

The evidenced thesis concerns UVM-based verification of RISC-V superscalar processors. Its abstract describes two proposed techniques intended to automate test application in a verification flow: a multi-armed bandit decision-making model for selecting constrained-random or direct test sequences, and a feedback-based mechanism for dynamically adjusting test application time. The abstract reports evaluation on a non-trivial design, specifically a 2-way superscalar out-of-order RISC-V processor.

Related person

The thesis names Assistant Professor Georgios Dimitrakopoulos as supervisor. This supports an academic association between Georgios Dimitrakopoulos and the Democritus University of Thrace context represented by the thesis document.

LINKED ENTITIES

1 links

CITATIONS

5 sources
5 citations
[1] A 2019 MSc thesis titled 'UVM-based verification of RISC-V superscalar processors: A reinforcement learning approach' is associated with Democritus University of Thrace. [PDF] UVM-based verification of RISC-V superscalar processors
[2] The thesis front matter lists the Department of Electrical and Computer Engineering and the Lab of Integrated Circuits under Democritus University of Thrace. [PDF] UVM-based verification of RISC-V superscalar processors
[3] Assistant Professor Georgios Dimitrakopoulos is named as supervisor of the thesis. [PDF] UVM-based verification of RISC-V superscalar processors
[4] The thesis abstract describes multi-armed bandit test-sequence selection and a feedback-based mechanism for adjusting constrained-random test application time. [PDF] UVM-based verification of RISC-V superscalar processors
[5] The thesis abstract states that the techniques were evaluated on a 2-way superscalar out-of-order RISC-V processor. [PDF] UVM-based verification of RISC-V superscalar processors