Zacharias Takakis

Person

Zacharias Takakis is documented as the author of the 2019 MSc thesis "UVM-based verification of RISC-V superscalar processors: A reinforcement learning approach" at Democritus University of Thrace. The thesis proposed reinforcement-learning-inspired methods for automating test application in UVM-based verification of a 2-way superscalar out-of-order RISC-V processor.

First seen 5/28/2026

Last seen 5/28/2026

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Zacharias Takakis

Overview

Zacharias Takakis is identified in the available evidence as the author of the MSc thesis "UVM-based verification of RISC-V superscalar processors: A reinforcement learning approach", dated May 22, 2019. The thesis was produced at the Democritus University of Thrace, Department of Electrical and Computer Engineering, in the BS Lab of Integrated Circuits, under the supervision of Assistant Professor Georgios Dimitrakopoulos.[1]

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LINKED ENTITIES

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Democritus University of Thrace degree_institution The thesis title page lists Democritus University of Thrace as the institution associated with Zacharias Takakis's MSc thesis.

Georgios Dimitrakopoulos thesis_supervisor The thesis title page states that Assistant Professor Georgios Dimitrakopoulos was the supervisor.

CITATIONS

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[1] Zacharias Takakis authored the MSc thesis titled "UVM-based verification of RISC-V superscalar processors: A reinforcement learning approach," dated May 22, 2019, at Democritus University of Thrace, Department of Electrical and Computer Engineering, BS Lab of Integrated Circuits, supervised by Assistant Professor Georgios Dimitrakopoulos. [PDF] UVM-based verification of RISC-V superscalar processors

[2] The thesis focuses on front-end functional verification, functional coverage, and reducing test application time. [PDF] UVM-based verification of RISC-V superscalar processors

[3] The thesis proposes using a multi-armed bandit decision-making model to select constrained-random or directed test sequences for improving functional coverage. [PDF] UVM-based verification of RISC-V superscalar processors

[4] The thesis proposes a feedback-based mechanism that dynamically adjusts test application time for constrained-random test sequences and replaces underperforming sequences. [PDF] UVM-based verification of RISC-V superscalar processors

[5] The experimental design discussed in the thesis is a 2-way superscalar out-of-order RISC-V processor, and the contents cover processor stages including instruction fetch, decode, register renaming, issue, execution, and writeback. [PDF] UVM-based verification of RISC-V superscalar processors

[6] The thesis states that automating test application improves functional coverage, minimizes verification effort, and shortens time to market. [PDF] UVM-based verification of RISC-V superscalar processors