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O'Hallaron

Person WIKI v1 · 5/25/2026

O'Hallaron is a person entry with a provided co-authorship relationship to Randal E. Bryant. The supplied technical evidence for this entry centers on formal verification of pipelined Y86-64 microprocessors using UCLID5, including safety-versus-liveness concerns, Burch-Dill correspondence checking, and UCLID5 modeling features.

Overview

O'Hallaron is represented here as a person entity. The provided relationship data identifies a co-authorship connection involving Randal E. Bryant.

Technical context in the supplied evidence

The supplied evidence is an excerpt from the technical report Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5. The report discusses verification of pipelined Y86-64 microprocessors and notes that safety checking alone can be insufficient: a processor that deadlocks, or even a device that does nothing, can pass a verification if the proof does not also establish liveness. The report therefore describes an approach for proving that the pipeline does not stall indefinitely.[1]

The excerpt describes UCLID5 as a formal verification tool with both a modeling language and a command language. In the reported verification setup, the modeled system combines a pipelined microprocessor with a sequential reference implementation, while the verification script specifies initialization, operation, and verification conditions for Burch-Dill correspondence checking.[2]

UCLID5 is described as supporting models that combine synchronous hardware and software. Hardware is modeled as state machines that compute and transition to next states, while software is modeled as sequences of operations that update system state. For the pipelined microprocessor verification discussed in the report, only UCLID5's hardware-modeling aspects were used.[3]

The report excerpt also lists UCLID5 data types relevant to hardware modeling, including uninterpreted terms and functions, integers, bit vectors, enumerated values, Booleans, tuples and records, and arrays. These types support modeling structures such as hardware blocks, registers, memories, operation codes, and branch-decision logic.[4]

Relationship

  • Co-authored relationship: Randal E. Bryant is provided as a related person connected to O'Hallaron by a CO_AUTHORED relationship.

[1]: Supplied evidence, chunk 6fb16f07-09d7-43b6-a1ac-67ee5531cfcc. [2]: Supplied evidence, chunk 6fb16f07-09d7-43b6-a1ac-67ee5531cfcc. [3]: Supplied evidence, chunk 6fb16f07-09d7-43b6-a1ac-67ee5531cfcc. [4]: Supplied evidence, chunk 6fb16f07-09d7-43b6-a1ac-67ee5531cfcc.

LINKED ENTITIES

1 links
Randal E. Bryant CO_AUTHORED

CITATIONS

4 sources
4 citations
[1] The supplied report argues that safety checking alone can miss deadlock and that liveness must be verified to show a pipeline does not stall indefinitely. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[2] UCLID5 provides a modeling language and command language, and the described verification setup combines a pipelined microprocessor with a sequential reference implementation for Burch-Dill correspondence checking. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[3] UCLID5 supports modeling of synchronous hardware and software, with hardware represented as state machines and software as sequences of state-updating operations. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[4] The UCLID5 excerpt lists modeling data types including uninterpreted terms, integers, bit vectors, enumerated values, Booleans, tuples and records, and arrays. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5