Overview

“Functional Verification of the POWER5 Microprocessor and POWER5 Multiprocessor Systems” is a paper on functional verification for the POWER5 microprocessor and POWER5 multiprocessor systems. The available evidence identifies it as a 2005 publication in IBM Journal of Research and Development.

Bibliographic details

• Authors: D. W. Victor, J. M. Ludden, R. D. Peterson, B. S. Nelson, W. K. Sharp, J. K. Hsu, B.-L. Chu, M. L. Behm, R. M. Gott, A. D. Romonosky, and S. R. Farago
• Year: 2005
• Venue: IBM Journal of Research and Development
• Volume / issue: 49(4/5)
• Pages: 541–554

Citation context

The paper appears as a referenced work in the bibliography of the AAAI 2006 paper hosted as AAAI06-287.pdf, titled “Constraint-Based Random Stimuli Generation for Hardware ...” in the supplied evidence.