University of Bremen Wiki

Overview

Within the provided evidence, the University of Bremen appears as the Institute of Computer Science, University of Bremen, 28359 Bremen, Germany on a processor-verification publication. In that paper, Niklas Bruns, Vladimir Herdt, and Rolf Drechsler are listed with the University of Bremen affiliation; Herdt and Drechsler are also listed with Cyber-Physical Systems, DFKI GmbH, while Eyck Jentzsch is listed with MINRES Technologies GmbH.[C1]

Technical research context in the evidence

Cross-level processor verification for RISC-V RTL

The 2022 paper “Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging” proposes a cross-level verification approach for processor verification at the Register-Transfer Level (RTL). Its foundation is a randomized, coverage-guided instruction stream generator that produces one endless and unrestricted instruction stream that evolves dynamically at runtime.[C1]

The approach uses an Instruction Set Simulator (ISS) as a reference model in a tight co-simulation setting. Coverage information is continuously updated based on the ISS execution state, and the method uses Coverage-guided Aging to smooth the coverage distribution of the randomized instruction stream over time. The paper states that this combination enables broad and deep coverage for finding intricate corner-case bugs in RTL processors, and reports a case study with an industrial pipelined 32-bit RISC-V processor.[C1]

The same evidence frames RISC-V as a representative instruction set architecture for the work, describing it as a free and open-source ISA that enables royalty-free processor design and implementation and uses a modular structure with optional standard instruction-set extensions around a mandatory base integer instruction set.[C1]

Instruction set simulator verification using coverage-guided fuzzing

The related paper “Verifying Instruction Set Simulators using Coverage-guided Fuzzing” proposes applying state-of-the-art coverage-guided fuzzing to ISS verification. The paper’s conclusion states that the approach integrates a novel functional coverage metric, complementing code coverage, and a mutation procedure tailored specifically for ISS verification.[C2]

The fuzzing implementation was built on top of LLVM-based libFuzzer and evaluated on three publicly available RISC-V ISSs. The paper reports that the fuzzer was effective in maximizing most coverage metrics and found new errors in every considered ISS, including one error in the official RISC-V reference simulator Spike.[C2]

Researchers explicitly supported by the evidence

The provided evidence explicitly lists the following people with the Institute of Computer Science, University of Bremen, on the 2022 cross-level processor-verification paper:

Niklas Bruns[C1]
Vladimir Herdt[C1]
Rolf Drechsler[C1]

Scope of this article

Earlier unsupported details about additional University of Bremen publications and affiliations have been omitted here. This article is limited to the supplied evidence and the provided related-entity context.