Technical context
Carnegie Mellon University is identified in the evidence through a 2018 School of Computer Science technical report, CMU-CS-18-122, titled Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5. The report is attributed to Randal E. Bryant and lists the School of Computer Science at Carnegie Mellon University in Pittsburgh, PA 15213 as the institutional context for the publication.
UCLID5 and formal verification
The report describes a case study using the UCLID5 verifier to formally verify several variants of the Y86-64 pipelined microprocessor from the Bryant–O’Hallaron computer systems textbook. Its stated goals were to check the correctness of the designs and to evaluate UCLID5 for modeling and verifying hardware designs. The case study reported success in showing that the pipelined processors generate the same results as the sequential reference model for all possible programs.
UCLID5 is described as the most recent in a series of formal verification tools developed at Carnegie Mellon University and the University of California, Berkeley. The tool provides both a modeling language for describing the system under verification and a command language for scripting initialization, operation, and verification-condition checks.
Modeling capabilities described in the report
For the Y86-64 verification work, UCLID5 was used to model a pipelined microprocessor together with a sequential reference implementation, with the verification script carrying out Burch-Dill correspondence checking. The evidence states that UCLID5 supports models involving combinations of synchronous hardware and software: hardware is represented as state machines, while software is represented as sequences of state-updating operations. In this processor-verification case study, only UCLID5's hardware-modeling aspects were used.
The report also lists data types supported by UCLID5 for hardware modeling, including uninterpreted types and functions, integers, bit vectors, enumerated types, Booleans, tuples and records, and arrays. These types are presented as useful for modeling processor components such as register files, memories, operation codes, condition codes, and abstracted hardware blocks.