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Accellera

Organization WIKI v1 · 5/27/2026

Accellera is identified in the evidence through its role in establishing the UVM standard, a SystemVerilog-based verification methodology developed through cooperation between EDA vendors and customers and informed by prior methodologies such as OVM and VMM.

Overview

Accellera is described in the available evidence as the organization behind the Accellera UVM standard. The standard was established through cooperation between EDA vendors and customers, using the existing OVM code base and contributions from VMM as important inputs.[1]

Role in UVM

The Accellera UVM standard combined experience and technologies from several earlier verification methodologies and libraries. The evidence describes UVM as a hybrid of technologies originating in Mentor's AVM, Mentor and Cadence's OVM, Verisity's eRM, and Synopsys's VMM-RAL, with additional technologies such as Resources, TLM, and Phasing.[2]

UVM is presented as a standardized methodology for verifying digital designs. It builds on SystemVerilog and provides a framework of SystemVerilog classes for constructing verification testbenches, including drivers, monitors, stimulus generators, and scoreboards.[3]

Purpose and impact

The Accellera UVM standard is characterized as a way to create scalable, reusable, and interoperable testbenches. The evidence also notes that OVM forms the core of UVM, allowing object-oriented design and methodology experience from OVM to be applied in UVM projects.[4]

The methodology addresses the verification challenges of increasingly complex systems, where verification environments may need to support functional verification workflows involving emulation, hardware acceleration, and FPGA prototyping.[5]

Related standards and methodologies

  • UVM: the Accellera standard discussed in the evidence, used for standardized digital-design verification with SystemVerilog-based testbench components.

LINKED ENTITIES

1 links
UVM INTRODUCES

CITATIONS

5 sources
5 citations
[1] The Accellera UVM standard was established through cooperation between EDA vendors and customers, with OVM code base and VMM contributions as inputs. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[2] UVM combined technologies from Mentor's AVM, Mentor and Cadence's OVM, Verisity's eRM, Synopsys's VMM-RAL, and newer technologies such as Resources, TLM, and Phasing. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[3] UVM is a standardized methodology for verifying digital designs, builds on SystemVerilog, and provides SystemVerilog classes for testbench components such as drivers, monitors, stimulus generators, and scoreboards. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[4] The combined UVM features support scalable, reusable, and interoperable testbenches, and OVM forms the core of UVM. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[5] UVM addresses verification challenges for increasingly complex systems and is discussed in the context of workflows that include emulation, hardware acceleration, and FPGA prototyping. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi