RVA22

ISA

RVA22 is identified in the evidence as a new RISC-V profile supported by a RISC-V processor verification flow aimed at future-ready compliance. The same source places RVA22 alongside RVA23 and mentions related verification coverage for privilege and extension areas such as MMU, PMP, hypervisor, and vector extensions.

First seen 5/25/2026

Last seen 5/25/2026

Evidence 1 chunks

Wiki v2

WIKI

Overview

RVA22 is a RISC-V profile named in the context of RISC-V processor verification and compliance readiness. The provided source states that a verification flow supports new RISC-V profiles, specifically RVA22 and RVA23.^[1]

Verification context

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NEIGHBORHOOD

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LINKED ENTITIES

2 links

RISC-V profile_of The evidence explicitly describes RVA22 as one of the new RISC-V profiles supported by the verification flow.

RVA23 sibling_profile The evidence names RVA22 and RVA23 together as new RISC-V profiles supported by the same flow.

CITATIONS

4 sources

4 citations — click to collapse

[1] RVA22 is identified as a new RISC-V profile, named alongside RVA23, in the context of a verification flow supporting future-ready compliance. source

[2] The verification flow is described as covering critical privilege specifications including MMU, PMP, hypervisor, and vector extensions. source

[3] The broader methodology combines constrained-random stimulus with directed suites to improve RISC-V verification coverage and compliance work. source

[4] The source describes test portability across simulation, emulation, FPGA prototyping, and silicon, supporting a shift-left verification methodology. source