Overview

vsetvli is discussed in the available evidence as an instruction that needed explicit generation in a RISC-V vector verification flow. The verification team modified RISCV-DV so generated assembly tests could include vsetvli instructions and so memory-operation generation could account for changes in element width and vector length.

Role in verification

In Functional Verification of a RISC-V Vector Accelerator, RISCV-DV was used to generate random RISC-V assembly tests for a vector processing unit (VPU). Because the RISCV-DV version available to the authors implemented a later RISC-V Vector Extension version than RVV 0.7.1, they adapted the needed parts of the tool.

A major addition was generation of vsetvli instructions through the generated code. This was paired with changes to memory-operation generation so tests could vary element width and vector length. The same RISCV-DV adaptation also included data-page initialization controls, constraints on memory addresses to avoid memory exceptions, and broader adaptation to RVV 0.7.1.

Related entities

• Functional Verification of a RISC-V Vector Accelerator — uses vsetvli generation as part of its vector-accelerator verification flow.
• RISCV-DV — the random RISC-V assembly test generator that was modified to generate vsetvli instructions in this work.