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STIMSMITH

vmm_data

CodeArtifact WIKI v1 · 5/28/2026

`vmm_data` is a VMM code artifact associated with standard data-object methods. In the provided constrained-random verification example, an `Instruction` class implements standard `vmm_data` methods, including display and packing behavior used as part of a transaction-class implementation.

Overview

vmm_data is referenced as the source of standard methods implemented by an Instruction transaction class in a constrained-random verification example for microprocessors. The cited example describes class methods as one of the components of a transaction class, alongside properties and constraints.

Use in an Instruction transaction class

The evidence describes transaction-class methods for displaying and packing instruction-related objects. It names opcode::psdisplay() and opcode::byte_pack() as example methods, and identifies the shown Instruction class implementation as an implementation of standard vmm_data methods.

Verification context

The same example places these methods in a larger constrained-random verification flow. The transaction class contains constraints that encode processor rules, such as slot restrictions for load/store operations and ERET, pairing requirements with NOP, and restrictions on writing the same scalar register from both operations of the same instruction. These constraints can be separated into independently controllable blocks so that tests can either obey or intentionally violate specific processor rules for exception testing.

CITATIONS

3 sources
3 citations
[1] The Instruction class is described as implementing standard vmm_data methods. Applying constrained-random verification to microprocessors
[2] The transaction-class method examples include display and byte-packing methods such as opcode::psdisplay() and opcode::byte_pack(). Applying constrained-random verification to microprocessors
[3] The constrained-random verification example uses transaction-class constraints to encode processor rules, including slot restrictions for load/store and ERET operations, ERET/NOP pairing, and disallowing writes to the same scalar register in both operations of the same instruction. Applying constrained-random verification to microprocessors