Overview

VHDL is referenced as a hardware description language alongside Verilog in the context of ITL-based formal properties for synchronous sequential systems. In ITL temporal expressions, standard operators from the respective HDL language—VHDL or Verilog—can be used together with temporal operators such as next and prev.[C1]

Data types and modeling use

The evidence highlights VHDL data-type support as part of ITL. ITL supports all data types of the respective HDL, including arrays, user-defined types, and nested record data types in VHDL.[C2]

In an architectural-style verification and simulator-generation workflow, the architectural state is established using a user-defined VHDL record data type. This record combines all parts of the architectural state; typical contents include a processor register file, status flags, and a program counter. New data types can likewise describe interfaces to memories and ports.[C3]

Role in processor verification and ISS generation

The cited work describes reformulating processor verification properties into an architectural style. When verification has already been carried out in that style, an instruction set simulator can be generated from the verification without manual steps in between.[C4]

The same workflow uses a next_state macro to capture the effects of instructions and interrupts on architectural state. The resulting reformulation produces a single property that captures the behavior of the verified design and yields a formally checkable ISA description, which is then used as the starting point for automatic generation of a C++ instruction set simulator.[C5]

Example scale

In one reported industrial-design experiment, the processor-core source code amounted to about 10,000 lines of VHDL, while the final reformulated property suite contained 2,000 lines of ITL. The property suite and its completeness were checked against the processor design.[C6]

Notes

Within the provided evidence, VHDL is not described broadly as a language standard or ecosystem. The supported claims are specifically about its use as an HDL in ITL expressions, its record and other data types in verification modeling, and its use in processor-core implementation code.