Overview

Verilog is a popular hardware description language used to model and design digital systems. Because of that role, automated generation of Verilog code is treated as an important step in automating hardware design workflows.[1]

Semantics and synthesizable Verilog

The Verilog standard defines simulation semantics, but recent formalisation work reports that these semantics have been difficult to formalise definitively for real-world hardware designs. The reported reason is that the standard is inconsistent both with Verilog practice and with itself. The same work focuses on the synthesizable subset of Verilog, described as the subset used to describe hardware designs, and presents repairs to an executable formalisation so that it can execute real-world hardware designs.[2]

Use in verification-oriented languages

Verilog is also relevant to property and temporal-logic based hardware verification. In ITL, temporal logic expressions describe the behaviour of synchronous sequential systems over discrete time steps corresponding to clock cycles. ITL temporal expressions can use the standard operators of the respective hardware description language, including Verilog, and can use HDL data types such as arrays.[3]

Related entities

• ITL: a temporal-logic based specification language whose expressions can use standard Verilog operators when targeting Verilog-based designs.[3]