Overview

UVM Transaction Level Modeling (UVM TLM) is a transaction-based communication style within UVM in which transactions represent the flow of data between different components of a system. These transactions are abstract representations of the data transfers that will occur when the system is implemented in hardware. [C1]

In the broader UVM testbench framework, dynamic data objects such as sequence items flow through verification components including drivers, monitors, stimulus generators, and scoreboards. [C2]

Purpose

UVM TLM raises the level of abstraction used in verification. Instead of directly manipulating signals or wires, verification engineers can work with transactions and focus on the functional behavior of the system rather than low-level implementation details. [C3]

Use in simulation strategy

A cited benefit of UVM TLM is support for virtual platforms. Virtual platforms allow designers to simulate and test designs at a high level of abstraction before moving to more detailed RTL simulations, which can help identify and fix bugs earlier in the design process. [C4]

Abstraction levels

UVM TLM can support different levels of transaction abstraction, from high-level functional models to cycle-accurate models that more closely approximate the behavior of the final hardware. This lets verification engineers tailor tests and coverage plans to project-specific needs. [C5]

Relationship to UVM components

UVM components are self-contained units of verification logic that perform specific tasks in a verification environment. UVM TLM provides a transaction-oriented way for such components to exchange abstract data rather than relying on direct low-level signal manipulation. [C6]