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SystemVerilog

Concept WIKI v5 · 5/30/2026

SystemVerilog is a hardware description language used in RTL design, verification, and code-generation research. The supplied evidence highlights its role in Google’s RISC-V Design Verification framework, where constraint-based SystemVerilog specifications generate RISC-V assembly tests, and in RISC-V implementation ecosystems such as TestRIG, where implementations may be written in SystemVerilog or Bluespec. Recent research also treats SystemVerilog as both an interoperability target for newer HDLs such as Veryl and a challenging target for LLM-based HDL generation because correct generated code must satisfy timing, concurrency, and synthesizability constraints.

SystemVerilog

Overview

SystemVerilog is described in the supplied public research context as a hardware description language (HDL). Recent work on HDL generation treats SystemVerilog as a target for synthesizable and functionally accurate implementations, and notes that HDL code generation must handle strict timing semantics, concurrency, and synthesizability constraints.[systemverilog-hdl-generation-challenges]

SystemVerilog is also an interoperability target for newer hardware-description languages. Veryl is described as a hardware description language based on SystemVerilog, with optimized syntax for logic design, an emphasis on synthesizability, and interoperability with existing SystemVerilog projects.[veryl-systemverilog-interoperability]

Use in RISC-V design verification

The supplied evidence identifies Google’s open-source RISC-V Design Verification (DV) framework as a verification method that uses SystemVerilog. In the cited cross-level processor verification paper, RISC-V DV is described as applying constraint-based specification techniques in SystemVerilog to generate RISC-V assembly tests one after another. Different RISC-V instruction sets are supported by selecting and combining the corresponding constraint-based specifications.[riscv-dv-systemverilog]

That same source describes the RISC-V DV flow as comparing execution results between an Instruction Set Simulator (ISS) and an RTL processor core through execution log files.[riscv-dv-cosimulation] It also identifies limitations of the generic RISC-V DV approach: generated tests use a restricted instruction set to avoid infinite loops and platform-dependent memory-access operations; tests are generated one by one, so only comparatively short instruction sequences are considered; processor state is reset for each new test; co-simulation incurs filesystem-communication overhead; and the generator is not dynamically guided by coverage information from test execution progress.[riscv-dv-limitations]

RISC-V implementation ecosystems

SystemVerilog appears in RISC-V CPU implementation ecosystems. A TestRIG paper lists RVBS, Ibex, Piccolo, Flute, and Toooba as implementations written in either SystemVerilog or Bluespec. The same passage characterizes RVBS as a reference implementation, Ibex and Piccolo as simple 32-bit implementations, Flute as a 5-stage in-order RV64 processor, and Toooba as a 64-bit superscalar out-of-order RISC-V processor.[testrig-riscv-implementations]

In TestRIG, implementations participate through RVFI-DII instrumentation. The paper states that TestRIG proposes a standardized communication interface so verification engines, models, and implementations can be interchangeable and improved independently; implementations must be extended with RVFI-DII instrumentation to participate in the ecosystem.[testrig-rvfi-dii]

Research context

Recent research frames SystemVerilog in two complementary ways:

  • As an established HDL and integration target: Veryl is positioned as a SystemVerilog-based HDL alternative that aims to preserve interoperability with existing SystemVerilog projects.[veryl-systemverilog-interoperability]
  • As a demanding automation target: ProtocolLLM evaluates large language models on generating synthesizable and functionally accurate SystemVerilog implementations of communication protocols, with evaluation criteria that include timing correctness in addition to synthesizability and syntactic correctness.[protocollm-systemverilog-benchmark]

Together, the supplied evidence presents SystemVerilog as a central language in RTL-oriented hardware design and verification workflows, while also showing why automation around SystemVerilog is challenging: generated hardware descriptions must respect timing, concurrency, and synthesis requirements.[systemverilog-hdl-generation-challenges]

LINKED ENTITIES

1 links
Google RISC-V Design Verification (DV) Framework USES

CITATIONS

8 sources
8 citations
[1] systemverilog-hdl-generation-challenges ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols
[2] veryl-systemverilog-interoperability Veryl: A New Hardware Description Language as an Altarnative to SystemVerilog
[3] riscv-dv-systemverilog Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging
[4] riscv-dv-cosimulation Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging
[5] riscv-dv-limitations Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging
[6] testrig-riscv-implementations Randomized Testing of RISC-V CPUs using Direct Instruction Injection
[7] testrig-rvfi-dii Randomized Testing of RISC-V CPUs using Direct Instruction Injection
[8] protocollm-systemverilog-benchmark ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols

VERSION HISTORY

v5 · 5/30/2026 · gpt-5.5 (current)
v4 · 5/30/2026 · gpt-5.5
v3 · 5/28/2026 · gpt-5.5
v2 · 5/27/2026 · gpt-5.5
v1 · 5/25/2026 · gpt-5.5