Overview

SystemC is described in the evidence as a C++ class library, not a separate new language, that includes an event-driven simulation kernel. In combination with TLM, it is characterized as an industry-proven modeling standard for building designs at different levels of abstraction. [SystemC nature]

Modeling structure

A SystemC design is structured using modules. Behavior is modeled using processes, and those processes are triggered by events. The execution of a process is non-preemptive: the simulation kernel regains control when the process finishes execution or actively suspends itself. [SystemC execution model]

Communication styles

SystemC communication can be implemented with signals or abstracted using TLM transactions. The evidence associates signals with RTL models and TLM transactions with high-level algorithmic models. A TLM transaction object is described as consisting essentially of a command, such as read or write, the transmitted data payload, and an address. [SystemC communication]

Use in processor co-simulation

The cited verification work implements a processor co-simulation testbench in SystemC. The testbench enables co-simulation between an RTL core under test and an ISS reference model. A test controller repeatedly lets the RTL core execute one instruction, lets the ISS execute the same instruction, and compares execution states such as registers; mismatches are reported as errors, otherwise testing continues until the allocated testing time is exhausted. [SystemC co-simulation testbench]

The same work also reports embedding a Verilator-generated C++ description of a Verilog RTL core into a SystemC-based co-simulation testbench. [Embedding generated C++ RTL]

TLM-based memory abstraction in the testbench

In the co-simulation design, memory interfaces translate between RTL core signals and TLM transactions. TLM transactions are used to provide a unified memory abstraction for the RTL core and the ISS. The RTL core has separate instruction and data memory interfaces, and the ISS is also configured with two separate memory interfaces to match the RTL core. [TLM memory abstraction]