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STIMSMITH

Stimulus Space Coverage

Concept WIKI v1 · 5/26/2026

Stimulus space coverage is a verification objective focused on efficiently generating and distributing test stimuli across meaningful values of opcodes and instruction attributes. In the provided evidence, it is addressed through automated random test generation, SystemVerilog constraints, weighted distributions, and hierarchical constrained-random generator architectures.

Definition

Stimulus space coverage refers to the verification goal of exercising the meaningful range of possible test stimuli for a design. In the microprocessor-verification context described in the evidence, this means generating microcode test sequences that distribute stimuli across meaningful values for opcodes and other instruction attributes.[1]

Role in microprocessor verification

As microprocessor designs become more complex, hand-written directed tests become less central, and automated random test generators are used to cover the stimulus space more efficiently.[2] These generators create microcode instruction sequences and emphasize control over how stimuli are distributed across opcode values and related instruction attributes.[1]

Distribution control

Traditional sequential randomization of instruction fields can produce verbose and redundant code and gives limited control over stimulus distributions.[3] The cited approach uses SystemVerilog constraint-language constructs to describe legal combinations of microcode-instruction attributes and to control the distribution of values for individual fields.[4]

A two-layer generator architecture is described:

  • The upper layer uses a SystemVerilog random sequence construct with weighted knobs to control distributions of high-level items.
  • The lower layer randomizes an opcode class with additional constraints and weights supplied by the upper layer.

In this architecture, tests provide weighted values that direct the required instruction mix, and the constraint solver applies those weights to control the distribution of generated opcode types.[5]

Constrained-random and hierarchical approaches

The evidence describes a hierarchical constrained-random method intended to accelerate generation, reduce memory consumption, improve distribution control, and bias generation toward corner cases.[6]

An initial single-class generator placed constraints for all opcodes in one class. This provided flexibility because constraints could be applied among any data members, but it made the constraint-solving problem large and potentially slow; the example opcode class contained approximately 100 random variables and 800 constraint equations.[7]

A later object-oriented approach introduced a base class for global opcode constraints and derived subclasses for related opcode groups with similar constraints. Partitioning constraints hierarchically into smaller opcode groups reduced memory requirements and improved performance.[8]

Practical significance

Stimulus space coverage is therefore not only about generating random tests, but about controlling the distribution of generated stimuli so that meaningful opcode and instruction-attribute combinations are exercised efficiently. Weighted constrained-random generation and hierarchical constraint partitioning are presented as techniques for improving coverage efficiency, controlling bias, and managing solver performance.[9]

[1]: See citation: "Stimulus space means meaningful opcode and instruction-attribute values." [2]: See citation: "Automated random generators replaced many directed tests as complexity increased." [3]: See citation: "Sequential randomization has redundancy and limited distribution control." [4]: See citation: "SystemVerilog constraints describe attribute combinations and field distributions." [5]: See citation: "Two-layer weighted generator architecture controls opcode-type distribution." [6]: See citation: "Hierarchical constrained-random generation targets speed, memory, distribution, and corner cases." [7]: See citation: "Single-class randomization is flexible but can be slow due to problem size." [8]: See citation: "Hierarchical opcode partitioning reduces memory and improves performance." [9]: See citations: "Hierarchical constrained-random generation targets speed, memory, distribution, and corner cases" and "Two-layer weighted generator architecture controls opcode-type distribution."

LINKED ENTITIES

1 links
Synopsys VCS Constraint Solver supports_weighted_constrained_random_generation

CITATIONS

9 sources
9 citations
[1] Stimulus space means meaningful opcode and instruction-attribute values. Generating AMD microcode stimuli using VCS constraint solver
[2] Automated random generators replaced many directed tests as complexity increased. Generating AMD microcode stimuli using VCS constraint solver
[3] Sequential randomization has redundancy and limited distribution control. Generating AMD microcode stimuli using VCS constraint solver
[4] SystemVerilog constraints describe attribute combinations and field distributions. Generating AMD microcode stimuli using VCS constraint solver
[5] Two-layer weighted generator architecture controls opcode-type distribution. Generating AMD microcode stimuli using VCS constraint solver
[6] Hierarchical constrained-random generation targets speed, memory, distribution, and corner cases. Generating AMD microcode stimuli using VCS constraint solver
[7] Single-class randomization is flexible but can be slow due to problem size. Generating AMD microcode stimuli using VCS constraint solver
[8] The cited single-class opcode generator contained approximately 100 random variables and 800 constraint equations. Generating AMD microcode stimuli using VCS constraint solver
[9] Hierarchical opcode partitioning reduces memory and improves performance. Generating AMD microcode stimuli using VCS constraint solver