Stimulus Space Coverage

Concept

Stimulus space coverage is a verification objective focused on efficiently generating and distributing test stimuli across meaningful values of opcodes and instruction attributes. In the provided evidence, it is addressed through automated random test generation, SystemVerilog constraints, weighted distributions, and hierarchical constrained-random generator architectures.

First seen 5/26/2026

Last seen 5/29/2026

Evidence 1 chunks

Wiki v1

WIKI

Definition

Stimulus space coverage refers to the verification goal of exercising the meaningful range of possible test stimuli for a design. In the microprocessor-verification context described in the evidence, this means generating microcode test sequences that distribute stimuli across meaningful values for opcodes and other instruction attributes.^[1]

Role in microprocessor verification

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LINKED ENTITIES

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Synopsys VCS Constraint Solver supports_weighted_constrained_random_generation The evidence describes using the Synopsys VCS constraint solver to provide distribution control, biasing, and application of weights in the generator.

CITATIONS

9 sources

9 citations — click to expand

[1] Stimulus space means meaningful opcode and instruction-attribute values. Generating AMD microcode stimuli using VCS constraint solver

[2] Automated random generators replaced many directed tests as complexity increased. Generating AMD microcode stimuli using VCS constraint solver

[3] Sequential randomization has redundancy and limited distribution control. Generating AMD microcode stimuli using VCS constraint solver

[4] SystemVerilog constraints describe attribute combinations and field distributions. Generating AMD microcode stimuli using VCS constraint solver

[5] Two-layer weighted generator architecture controls opcode-type distribution. Generating AMD microcode stimuli using VCS constraint solver

[6] Hierarchical constrained-random generation targets speed, memory, distribution, and corner cases. Generating AMD microcode stimuli using VCS constraint solver

[7] Single-class randomization is flexible but can be slow due to problem size. Generating AMD microcode stimuli using VCS constraint solver

[8] The cited single-class opcode generator contained approximately 100 random variables and 800 constraint equations. Generating AMD microcode stimuli using VCS constraint solver

[9] Hierarchical opcode partitioning reduces memory and improves performance. Generating AMD microcode stimuli using VCS constraint solver