Definition
Shift-Left Verification is a methodology in which test generation and validation are moved earlier in the design cycle. The supplied evidence describes this in the context of RISC-V processor verification, where portable stimulus allows tests to start in simulation and then be reused in emulation, FPGA prototyping, and silicon, reducing late-stage risk. [C1]
Role in the Verification Flow
In a shift-left flow, tests developed during RTL bring-up are not discarded after early simulation. Instead, they remain valuable throughout later validation stages and can continue to be used even in silicon. [C2]
The methodology is closely tied to portability: evidence describes tests as portable across simulation, ZeBu emulation, HAPS FPGA prototyping, and silicon. This portability is what enables the same verification intent to be applied earlier and then carried forward into later execution platforms. [C3]
Coverage and Pre-RTL Use
Shift-left verification is also connected to earlier coverage visibility. The evidence states that ImperasSC enables pre-RTL coverage analysis, moving validation earlier in the flow and allowing coverage growth to begin before RTL maturity. [C4]
This makes shift-left verification complementary to coverage-closure practices: early stimulus-coverage insight can expose gaps before the RTL is fully mature, while later simulation, emulation, prototyping, and silicon runs can reuse the same portable tests. [C4]
Benefits Reported in the Evidence
The supplied evidence identifies several benefits for RISC-V verification teams:
- Portability and shift-left enablement: tests can run across simulation, emulation, FPGA prototyping, and silicon. [C3]
- Earlier validation: ImperasSC supports pre-RTL stimulus coverage, moving validation earlier in the flow. [C4]
- Reduced late-stage risk: portable stimulus enables tests to start in simulation and be reused in later platforms, which the evidence associates with reduced late-stage risk. [C1]
- Lifecycle reuse: tests developed during RTL bring-up remain useful throughout later validation and silicon. [C2]
Related Concepts and Tools
- RTL: Shift-left verification targets RTL bring-up by enabling tests created at that stage to remain useful later in the validation lifecycle. [C2]
- ImperasSC: ImperasSC is identified as enabling pre-RTL coverage analysis and shift-left validation. [C4]
- STING: STING is described as generating portable, self-checking RISC-V programs that can run across simulation, emulation, FPGA prototypes, and silicon. [C5]
- ZeBu and HAPS: These are named execution platforms for portable tests in the described verification flow: ZeBu for emulation and HAPS for FPGA prototyping. [C3]