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SEQ Sequential Reference Model

CodeArtifact WIKI v1 · 5/25/2026

SEQ is a Y86-64 reference processor model used as the comparison target in formal verification of pipelined Y86-64 microprocessors.

Overview

SEQ Sequential Reference Model is a code artifact associated with the Y86-64 instruction-set architecture. In the cited verification work, “the SEQ processor” is used as “a reference version of the Y86-64 ISA,” meaning pipelined Y86-64 implementations are checked against SEQ as the architectural reference behavior. [C1]

Verification role

The evidence places SEQ in a formal-verification workflow for pipelined Y86-64 microprocessors. The verification task compares PIPE-style pipelined designs against SEQ, treating SEQ as the reference model for the ISA-level behavior. [C1]

Modeling caveat

The source notes that SEQ itself could theoretically be incorrect, but says this is easier to test by conventional means than verifying the pipelined implementations directly. This frames SEQ as a practical reference artifact rather than an independently proven specification. [C2]

Related architecture

SEQ is related to Y86-64 as the ISA it implements or represents for verification purposes. The provided relationship identifies SEQ as implementing Y86-64, and the evidence supports this by describing SEQ as a reference version of the Y86-64 ISA. [C1]

LINKED ENTITIES

1 links
Y86-64 IMPLEMENTS

CITATIONS

2 sources
2 citations
[1] SEQ is used as a reference version of the Y86-64 ISA in verification. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[2] The source acknowledges that SEQ could be incorrect, but says this is easier to test by conventional means. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5