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Rocket Chip SoC Generator

Concept WIKI v1 · 5/29/2026

Rocket Chip SoC Generator is a framework referenced in processor-verification research as the generator used for the Rocket Core and BOOM Core RISC-V processors. The cited evidence identifies Rocket as an open-source, general-purpose, in-order RISC-V core and BOOM as an out-of-order, superscalar RISC-V core, both associated with the same Rocket Chip SoC Generator framework and Chisel-based design flows.

Overview

The Rocket Chip SoC Generator is described in the available evidence as a framework used to generate RISC-V processor cores. In the ProcessorFuzz evaluation, the authors state that the Rocket Core is an open-source, general-purpose, in-order RISC-V processor core that can be generated using the Rocket Chip SoC Generator framework. The same source states that the BOOM Core is an out-of-order, superscalar RISC-V processor core that can also be generated from the same framework. [generator-cores]

Generated cores mentioned in the evidence

  • Rocket Core: an open-source, general-purpose, in-order RISC-V processor core that can be generated using Rocket Chip SoC Generator. [rocket-core]
  • BOOM Core: an out-of-order, superscalar RISC-V processor core that can also be generated from the Rocket Chip SoC Generator framework. [boom-core]

Design-flow context

The evidence associates Rocket and BOOM with Chisel-based hardware design. It states that BOOM is designed in Chisel HDL and notes that FIRRTL is an intermediate representation used by Chisel HDL, which is used to design Rocket and BOOM cores. This Chisel/FIRRTL context is relevant because the cited ProcessorFuzz paper compares fuzzing approaches on Rocket and BOOM and discusses DIFUZZRTL register-coverage passes tailored for FIRRTL. [chisel-firrtl-context]

Verification and fuzzing context

In the cited ProcessorFuzz evaluation, Rocket and BOOM were used as processor targets for fuzzing experiments, with Spike used as the ISA reference model for correctness checking during fuzzing. The paper reports using commit version 148d5d2 for both Rocket and BOOM in those experiments. [fuzzing-context]

LINKED ENTITIES

4 links
Rocket Core DEPENDS_ON
BOOM Core DEPENDS_ON
Rocket Core GENERATES
BOOM core GENERATES

CITATIONS

5 sources
5 citations
[1] generator-cores: Rocket Chip SoC Generator is a framework used to generate Rocket Core and BOOM Core. ProcessorFuzz: Processor Fuzzing with Control and
[2] rocket-core: Rocket Core is an open-source, general-purpose, in-order RISC-V processor core that can be generated using the Rocket Chip SoC Generator framework. ProcessorFuzz: Processor Fuzzing with Control and
[3] boom-core: BOOM Core is an out-of-order, superscalar RISC-V processor core that can also be generated from the Rocket Chip SoC Generator framework. ProcessorFuzz: Processor Fuzzing with Control and
[4] chisel-firrtl-context: BOOM is designed in Chisel HDL, and FIRRTL is an intermediate representation used by Chisel HDL, which is used to design Rocket and BOOM cores. ProcessorFuzz: Processor Fuzzing with Control and
[5] fuzzing-context: In the ProcessorFuzz evaluation, Spike was used as the reference model for Rocket and BOOM fuzzing, and commit version 148d5d2 was used for both cores. ProcessorFuzz: Processor Fuzzing with Control and