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Register Alias Table

Concept WIKI v1 · 5/28/2026

A Register Alias Table (RAT) is a hardware table in a register-renaming stage that records the most recent mapping from each logical register specifier to a physical destination register, enabling source operands to be renamed before dispatch to the reservation station.

Definition

A Register Alias Table (RAT) is a hardware table used in a processor's register-renaming stage. It holds the most recent mapping of each logical register specifier to a physical destination register (Pdst). During renaming, the RAT is used to rename an instruction's logical source registers into physical register specifiers. The resulting physical register identifiers are forwarded to the reservation station so the instruction can determine when it is ready to execute.

Role in register renaming

In the described register-renaming design, instructions contain logical register specifiers: typically a logical destination register and two logical source registers. Register renaming replaces these logical specifiers with physical register specifiers. The destination physical register is allocated from a free list, while the RAT supplies the current physical mappings for source logical registers.

The register-renaming stage described in the evidence includes three hardware arrays:

  • Free List (FL): provides free physical destination registers for newly renamed destination operands.
  • Register Alias Table (RAT): stores the latest logical-to-physical mappings and is used for source-operand renaming.
  • Checkpoint Table (CKPT): stores snapshots of the RAT, including snapshots taken when branch instructions are encountered.

Checkpointing and recovery

The RAT can be checkpointed to support recovery after pipeline flushes. When a mispredicted branch causes a flush, the register-renaming state is restored using the checkpoint associated with the branch. In that recovery process, the RAT is restored from the checkpoint, and physical destination registers allocated after the offending instruction are returned to the free list.

LINKED ENTITIES

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Register Renaming PART_OF

CITATIONS

4 sources
4 citations
[1] A Register Alias Table is a table with the most recent mapping of each logical register specifier to a physical destination register. [PDF] UVM-based verification of RISC-V superscalar processors
[2] The RAT is used to rename input/source logical registers, and the renamed physical destination identifiers are forwarded to the reservation station to help determine when an instruction can execute. [PDF] UVM-based verification of RISC-V superscalar processors
[3] In the described register-renaming stage, the hardware arrays include the Free List, Register Alias Table, and Checkpoint Table. [PDF] UVM-based verification of RISC-V superscalar processors
[4] The Checkpoint Table stores snapshots of the RAT, and on a mispredicted-branch flush the RAT is restored from the checkpoint while physical destination registers allocated after the offending instruction are returned to the Free List. [PDF] UVM-based verification of RISC-V superscalar processors