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Machine mode (RISC-V privileged architecture)

Concept WIKI v1 · 5/26/2026

Machine mode is identified in the provided evidence as the mandatory execution mode of the RISC-V privileged architecture. The privileged architecture covers environment interaction, operating-system execution, and trap handling, and associates execution modes such as Machine mode with Control and Status Register (CSR) descriptions.

Overview

In the RISC-V privileged architecture, Machine mode is described as a mandatory execution mode. The privileged architecture covers functionality needed for environment interaction, operating-system execution, and trap handling, and it includes different execution modes with corresponding Control and Status Register (CSR) descriptions.

Role of CSRs

The evidence characterizes CSRs as special-purpose registers that form the backbone of the privileged architecture description. Machine-mode-related implementations may support an unprivileged base ISA together with Machine mode CSRs; one evaluated RTL core, for example, supported the RV32I ISA in combination with Machine mode CSRs.

Example CSRs named in the evidence include:

CSR Function described in the evidence
MISA Provides the supported instruction set.
MTVEC Stores the trap-handler address and access configuration.
MTVAL Provides exception-specific information in case of a trap.
MEPC Stores the return address from a trap for the MRET instruction.
MINSTRET Counts the number of retired instructions.
MHARTID Provides the read-only core ID.
MSTATUS Main control and status register for the core.

CSRs can be read-only and can consist of fields. A field is described as having a start position, bit width, and access specification, with WARL listed as an example access specification.

Verification relevance

The cited verification study reports that mismatches were mostly related to the RISC-V privileged ISA, particularly CSR handling, even though the tested RTL core had a mature implementation of the unprivileged ISA. The same study reports ten total bugs in the RTL core, including a case where writing to a read-only CSR did not cause an illegal-instruction trap. This makes Machine mode CSR behavior a significant target for processor verification in the evidence provided.

The study also describes randomized CSR-access instruction sequences: such a sequence performs a randomized CSR access and then writes the CSR value into a normal register so it can be compared with the instruction-set simulator register.

LINKED ENTITIES

2 links
Control and Status Register (CSR) uses
trap handling supports

CITATIONS

8 sources
8 citations
[1] Machine mode is a mandatory execution mode in the RISC-V privileged architecture.
[2] The RISC-V privileged architecture covers environment interaction, operating-system execution, and trap handling.
[3] CSRs are special-purpose registers and form the backbone of the privileged architecture description.
[4] Example CSRs include MISA, MTVEC, MTVAL, MEPC, MINSTRET, MHARTID, and MSTATUS, with the functions described in the article table.
[5] CSRs can be read-only and can contain fields with a start position, bit width, and access specification such as WARL.
[6] One evaluated RTL core supported the RV32I ISA in combination with Machine mode CSRs.
[7] In the cited verification study, most bugs were related to the RISC-V privileged ISA, particularly CSR handling, and ten total bugs were found in the RTL core.
[8] A CSR access sequence in the study performs randomized CSR access and writes the CSR value into a normal register for comparison with the ISS register.