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Interrupt

Concept WIKI v1 · 6/6/2026

In the Ibex verification flow, an interrupt is an external stimulus that causes a trap handled by dedicated interrupt handler code. ISS golden models cannot natively model interrupts, so a RISCV-DV handshaking mechanism is used together with a modified trace-log comparison to verify correct interrupt handling.

Definition

In the Ibex core verification context, an interrupt is a form of external stimulus that triggers a trap in the core. Together with debug requests and memory faults, interrupts are the principal class of asynchronous, externally-driven events that the RTL/ISS co-simulation flow must cover [chunk:9a950617-e250-431d-8371-91884e237d19].

Why ISS Models Cannot Model Interrupts

The standard end-to-end RTL/ISS co-simulation flow compares every register writeback produced by the Ibex RTL against the writebacks produced by a golden-model instruction set simulator (ISS). This works for ordinary instruction execution, but it falls apart once external stimulus such as interrupts is introduced, because ISS models can simulate traps due to exceptions but cannot model traps due to external stimulus [chunk:9a950617-e250-431d-8371-91884e237d19].

Verification Approach for Interrupts

To provide coverage for interrupt scenarios, the Ibex testbench relies on the handshaking mechanism provided by the RISCV-DV instruction generator. This mechanism allows the core to send status information to the testbench during program execution, enabling the testbench to verify that the core has entered the proper interrupt handler, entered Debug Mode properly, updated any CSRs correctly, and so on [chunk:9a950617-e250-431d-8371-91884e237d19].

Key details of the handshaking setup:

  • The signature address used by the testbench for the handshaking is 0x8ffffffc [chunk:9a950617-e250-431d-8371-91884e237d19].
  • A small set of API tasks is provided in dv/uvm/core_ibex/tests/core_ibex_base_test.sv to enable easy and efficient integration of the handshake mechanism [chunk:9a950617-e250-431d-8371-91884e237d19].
  • Real usage during simulations can be seen in dv/uvm/core_ibex/tests/core_ibex_test_lib.sv (the core_ibex_test_lib code artifact). The mechanism is extensively used to provide runtime verification for situations involving external debug requests, interrupt assertions, and memory faults [chunk:9a950617-e250-431d-8371-91884e237d19].
  • The full handshake mechanism is documented in the RISCV-DV project at https://github.com/google/riscv-dv/blob/master/docs/source/handshake.rst [chunk:9a950617-e250-431d-8371-91884e237d19].

Trace Log Comparison Around Interrupts

On top of the handshaking mechanism, a modified version of trace log comparison is used. Comparing every register write performed during the entire simulation would yield incorrect results, because the ISS trace log does not contain any execution information for code executed in the debug ROM or in any interrupt handler code [chunk:9a950617-e250-431d-8371-91884e237d19].

To address this, the flow compares only the final values contained in every register at the end of the test. This works because any code executed in the debug ROM and trap handlers — including interrupt handlers — should not corrupt register state in the rest of the program [chunk:9a950617-e250-431d-8371-91884e237d19].

Relationship to Other Concepts

  • External stimulus: Interrupts are a subclass of external stimulus. While ISS models can simulate traps due to exceptions, they cannot model traps due to external stimulus such as interrupts [chunk:9a950617-e250-431d-8371-91884e237d19].
  • core_ibex_test_lib.sv: This test-library code artifact is where the handshaking mechanism (and therefore interrupt-handling verification) is put into practice for real simulations [chunk:9a950617-e250-431d-8371-91884e237d19].

LINKED ENTITIES

2 links
external stimulus PART_OF
core_ibex_test_lib.sv USES

CITATIONS

6 sources
6 citations
[1] Interrupts are a form of external stimulus in the Ibex verification flow, alongside debug requests and memory faults. Verification — Ibex Documentation 0.1.dev50+g9742d89f5
[2] ISS models can simulate traps due to exceptions but cannot model traps due to external stimulus such as interrupts, which breaks standard RTL/ISS trace log comparison. Verification — Ibex Documentation 0.1.dev50+g9742d89f5
[3] The Ibex testbench uses the RISCV-DV handshaking mechanism to verify that the core has entered the proper interrupt handler, entered Debug Mode properly, and updated any CSRs correctly. Verification — Ibex Documentation 0.1.dev50+g9742d89f5
[4] The testbench uses handshake signature address 0x8ffffffc, with API tasks provided in dv/uvm/core_ibex/tests/core_ibex_base_test.sv. Verification — Ibex Documentation 0.1.dev50+g9742d89f5
[5] The handshaking mechanism is extensively used in dv/uvm/core_ibex/tests/core_ibex_test_lib.sv to provide runtime verification for interrupt assertions, external debug requests, and memory faults. Verification — Ibex Documentation 0.1.dev50+g9742d89f5
[6] Trace log comparison is modified to compare only the final values in every register at the end of the test, because the ISS trace log does not contain execution information for interrupt handler or debug ROM code. Verification — Ibex Documentation 0.1.dev50+g9742d89f5