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interrupt stimulus

Concept WIKI v1 · 5/28/2026

Interrupt stimulus is a verification stimulus used in the Ibex UVM testbench to exercise a CPU core's interrupt handling by driving signals onto the core's interrupt pins during test execution.

Definition

In the Ibex UVM verification environment, interrupt stimulus refers to external testbench activity that drives interrupt-related signals into the core under test. The documented interrupt agent is specifically described as driving stimulus onto the Ibex core's interrupt pins randomly during test execution.

Role in the Ibex testbench

The Ibex testbench stimulates the core to execute a program stored in memory, compares the core trace log against a Spike instruction-set-simulator trace log, and collects instruction and operand coverage. Within this environment, interrupt stimulus is one of the external stimuli used to exercise core behavior beyond ordinary instruction execution.

The interrupt agent is the component identified for this purpose: it drives interrupt stimulus onto the Ibex core's interrupt pins randomly while tests are running. The test and sequence library also includes sequences used to drive interrupt and debug stimulus into the core.

Verification context

Interrupt behavior is part of the broader Ibex verification scope. The cited testplan discussion lists exception and interrupt testing alongside RV32IMCB instruction testing, privileged-spec compliance, and debug-mode operation. In the co-simulation system, interrupt and debug requests observed in RTL simulation are forwarded to the Spike ISS so that the ISS and RTL remain synchronized.

LINKED ENTITIES

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CITATIONS

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4 citations
[1] In the Ibex UVM environment, interrupt stimulus is driven onto the Ibex core's interrupt pins randomly during test execution. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[2] The Ibex testbench stimulates the core to execute a program in memory, compares the core trace log against a Spike ISS trace log, and collects coverage information. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[3] Ibex test sequences are used to drive interrupt and debug stimulus into the core. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[4] The Ibex verification plan includes exception and interrupt testing, and the co-simulation system forwards observed interrupt and debug requests from RTL simulation to the Spike ISS to keep the models synchronized. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi