Overview

Instruction set simulation is represented in the evidence by the use of an ISA simulator as a software reference model during hardware verification. The reference model predicts how the design should behave from its inputs, accepts instructions as input, and generates expected results for comparison with the hardware design under verification.

Use in verification

In the cited RISC-V vector accelerator verification work, instruction set simulation was integrated into a UVM-based verification environment. A UVM scoreboard compared the vector processing unit's results with results produced by the reference model. The paper states that Spike, the RISC-V ISA simulator, was selected for co-simulation in that UVM environment.

The same work describes the verification infrastructure as performing step-by-step co-simulation of vector instructions using Spike as the reference model. It also reports that each completed vector instruction was compared against the reference model during co-simulation of constrained-random binaries and C programs.

Example implementation

Spike is identified in the evidence as a RISC-V ISA, or instruction set, simulator. In this context, Spike implements instruction set simulation for RISC-V and was used to provide expected architectural results during verification of a RISC-V vector accelerator.