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Hardware Description Language

Concept WIKI v3 · 6/8/2026

A hardware description language (HDL) is a class of language used to express hardware designs at the Register-Transfer Level (RTL), with Verilog and VHDL cited as examples. In the cited processor-fuzzing evidence, HDL-based designs are evaluated through RTL simulation rather than direct host execution, and HDL choice can determine which verification tools and metrics are applicable. The cited evidence names Chisel and SystemVerilog as two HDLs in which open-source RISC-V processors are designed, and contrasts HDL-coupled fuzzers (RFUZZ, Li et al.) with HDL-agnostic ones (ProcessorFuzz).

Overview

A hardware description language (HDL) is a language used to express hardware designs at the Register-Transfer Level (RTL). In the cited evidence, hardware (e.g., a processor) is not directly executable on a host machine; instead, a hardware design is implemented with an RTL abstraction and simulated with an RTL simulator to evaluate each test input. The RTL design is usually expressed with an HDL, with Verilog and VHDL given as examples. [C1][C2]

HDLs in processor verification

HDLs appear in the cited evidence as the implementation form for processor designs evaluated by coverage-guided hardware fuzzers. The ProcessorFuzz paper evaluates "a variety of widely-used open-source RISC-V based processors designed in different HDLs (i.e., Chisel and SystemVerilog)". [C1] A figure in the evidence shows the Rocket Core RTL as a representative example of an HDL-based processor design together with coverage-map outputs over its sub-modules. [C2]

HDL-agnostic versus HDL-coupled tools

The cited evidence highlights that HDL choice can determine which verification approaches are applicable:

  • HDL-coupled tools. "Both RFUZZ and Li et al. are highly coupled to Chisel HDL which limits the applicability of the approach." Monitoring multiplexers in complex designs with these tools can also introduce excessive performance overhead. [C3]
  • HDL-agnostic tools. "ProcessorFuzz is agnostic to HDL, which makes it both practical and efficient." [C3]
  • HDL-to-software translation. Trippel et al. translate hardware designs to software models so that software-style coverage metrics (e.g., basic block, edge) can be reused, but doing so introduces challenges such as proving the equivalence between the hardware design and the software model. [C3]
  • Industrial tooling. TheHuzz relies on coverage metrics extracted using industrial-standard tools such as Cadence and ModelSim, and reuses software-testing metrics (statement, branch, line, expression) that the evidence reports as insufficient for processor verification. [C3]

Related HDLs named in the evidence

  • Chisel HDL is named alongside SystemVerilog as one of the HDLs in which the evaluated open-source RISC-V processors are designed. [C1]
  • SystemVerilog HDL is named alongside Chisel as one of the HDLs in which the evaluated open-source RISC-V processors are designed. [C1]

Differential testing and simulation speed

In the cited fuzzing workflow, the same test input is provided to both an RTL simulator (running the HDL-based design) and a reference model, which is an ISA simulator that mimics the behavior of all ISA-level operations. Mismatches between the two outputs are treated as potential bugs, an instance of differential testing. The evidence further notes that "ISA simulation is 79× faster than RTL simulation for the open-source RISC-V based BOOM processor", motivating the use of the faster ISA simulation in the feedback loop. [C2]

Broader HDL research context

Public sources describe additional HDL research directions beyond the ProcessorFuzz evaluation:

  • Veryl is a hardware description language based on SystemVerilog that offers optimized syntax tailored for logic design, ensures synthesizability, and prioritizes interoperability with SystemVerilog to allow smooth integration with existing projects. It also ships with a set of development-support tools such as package managers and real-time checkers. [C4]
  • Board-level HDLs have been proposed as a way to increase automation and raise the level of abstraction for designing electronics. Such systems borrow programming-language concepts like generators and type systems while still needing to be designed with human factors in mind for existing hardware engineers. [C5]

LINKED ENTITIES

2 links
Chisel HDL PART_OF
SystemVerilog HDL PART_OF

CITATIONS

6 sources
6 citations
[1] A hardware design is implemented with an RTL abstraction and simulated with an RTL simulator to evaluate a test input, and the RTL design is usually expressed with an HDL (e.g., Verilog, VHDL). ProcessorFuzz: Processor Fuzzing with Control and Status Register Awareness
[2] ProcessorFuzz evaluates a variety of widely-used open-source RISC-V based processors designed in different HDLs (i.e., Chisel and SystemVerilog), and the Rocket Core RTL is shown as a representative HDL-based design. ProcessorFuzz: Processor Fuzzing with Control and Status Register Awareness
[3] RFUZZ and Li et al. are highly coupled to Chisel HDL which limits applicability; ProcessorFuzz is agnostic to HDL; Trippel et al. translate hardware designs to software models; TheHuzz relies on Cadence and ModelSim and software-style coverage metrics. ProcessorFuzz: Processor Fuzzing with Control and Status Register Awareness
[4] The fuzzing workflow applies differential testing between an RTL simulator running the HDL-based design and a reference model that is an ISA simulator, and ISA simulation is 79× faster than RTL simulation for the BOOM processor. ProcessorFuzz: Processor Fuzzing with Control and Status Register Awareness
[5] Veryl is a hardware description language based on SystemVerilog that provides optimized syntax for logic design, ensures synthesizability, prioritizes interoperability with SystemVerilog, and ships with development-support tools such as package managers and real-time checkers. Veryl: A New Hardware Description Language as an Alternative to SystemVerilog
[6] Board-level HDLs are explored to increase automation and raise the level of abstraction for electronics design, borrowing programming-language concepts such as generators and type systems while accounting for human factors. Opportunities and Challenges for Circuit Board Level Hardware Description Languages

VERSION HISTORY

v3 · 6/8/2026 · minimax/minimax-m3 (current)
v2 · 5/29/2026 · gpt-5.5
v1 · 5/28/2026 · gpt-5.5