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STIMSMITH

fence.i Instruction

Concept WIKI v1 · 5/26/2026

The fence.i instruction is identified in the evidence as a RISC-V instruction used to synchronise instruction and data streams. In RISC-V verification, mishandling of fence.i is cited as one class of issue exposed by constrained-random stimulus generated with STING.

Overview

The fence.i instruction is a RISC-V instruction used to synchronise instruction and data streams.[C1]

Verification relevance

In the cited RISC-V verification context, constrained-random stimulus generated by STING has exposed issues including mishandling of the fence.i instruction.[C2] The same evidence describes STING as a bare-metal, software-driven RISC-V test generator that produces C++-based random streams and ASM-style directed tests.[C3]

Context in RISC-V testing

The evidence frames fence.i mishandling as an example of a bug class that can be found through constrained-random testing. It argues that random and directed testing are complementary in RISC-V verification: random stimulus helps uncover unexpected behaviours, while directed suites help systematically target specification-related gaps.[C4]

References

  • [C1] Evidence chunk e79e3ecb-a829-4ced-b719-7d329fb97e3b
  • [C2] Evidence chunk e79e3ecb-a829-4ced-b719-7d329fb97e3b
  • [C3] Evidence chunk e79e3ecb-a829-4ced-b719-7d329fb97e3b
  • [C4] Evidence chunk e79e3ecb-a829-4ced-b719-7d329fb97e3b

LINKED ENTITIES

3 links
RISC-V instruction_set_context
STING verification_tool_exposes_issues
constrained-random test generation verification_method_context

CITATIONS

4 sources
4 citations
[1] The fence.i instruction is used in RISC-V to synchronise instruction and data streams. # **Introduction**
[2] STING has exposed issues including mishandling of the fence.i instruction. # **Introduction**
[3] STING is described as a bare-metal, software-driven RISC-V generator producing C++-based random streams and ASM-style directed tests. # **Introduction**
[4] The evidence presents random stimulus and directed suites as complementary approaches in RISC-V verification. # **Introduction**