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Debug Transport Module

Concept WIKI v1 · 5/27/2026

A Debug Transport Module (DTM) is used in common RISC-V verification infrastructure to load test binaries into RTL simulations and generate artificial system calls. Evidence from a RISC-V co-simulation study reports that memory-mapped DTM interaction can introduce nondeterministic architectural state and false-positive co-simulation mismatches; the same study notes that Dromajo supports DTM but can avoid it by using memory and bootrom checkpoints.

Overview

A Debug Transport Module (DTM) is described in the provided evidence as part of a common RISC-V verification infrastructure. In that setting, DTM is used to load test binaries into RTL and to generate artificial system calls.

Role in RISC-V verification

The cited MICRO-54 paper describes DTM as common in RISC-V verification flows. Its role is practical: it provides a mechanism for the simulation infrastructure to place binaries into the RTL environment and support artificial system-call behavior during test execution.

Determinism concerns

The same paper reports an important verification caveat: using DTM can bring the core into a nondeterministic architectural state, which led to false-positive co-simulation mismatches in the authors' experiments. The reported cause is that interaction with the host device through the memory-mapped DTM is sensitive to the characteristics and utilization of the machine running the simulator. As a result, simulations using DTM may sometimes be nondeterministic.

Relationship to Dromajo

The paper notes that Dromajo supports DTM because DTM is common in RISC-V verification infrastructure. However, Dromajo can also create memory and bootrom checkpoints, which can make DTM unnecessary in that flow. The authors further report that avoiding DTM can speed up simulation because the flow no longer spends time uploading the binary through DTM.

LINKED ENTITIES

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CITATIONS

4 sources
4 citations
[1] DTM is used in common RISC-V verification infrastructure to load test binaries to RTL and generate artificial system calls. [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...
[2] Use of DTM can bring the core into a nondeterministic architectural state and cause false-positive co-simulation mismatches. [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...
[3] Memory-mapped DTM interaction can be sensitive to the simulator host machine's characteristics and utilization, making simulations sometimes nondeterministic. [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...
[4] Dromajo supports DTM, but its memory and bootrom checkpoint capability can make DTM unnecessary and can speed simulation by avoiding binary upload time. [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...