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Branch History Table

Concept WIKI v1 · 5/28/2026

A Branch History Table (BHT) is a component of a processor branch predictor that records prior branch outcomes and uses them to predict whether current branch instructions will be taken or not taken. In the cited RISC-V superscalar processor instruction-fetch unit, the BHT is part of the dynamic predictor and uses a GShare indexing scheme; one verified implementation has 256 BHT entries.

Overview

A Branch History Table (BHT) is a branch-prediction structure used to maintain a history of the outcomes of previous occurrences of each branch. The stored history is used to predict the direction of a current branch instruction, i.e. whether it will be taken or not taken. In the cited RISC-V superscalar processor, the BHT uses a GShare indexing scheme. [citation: BHT purpose and indexing]

Role in instruction fetch

In the cited processor organization, the Instruction Fetch Unit fetches instructions from the instruction cache and predicts the next Program Counter (PC), the address of the next instruction to fetch. The dynamic predictor is described as an instrumental part of this instruction-fetch unit, and the BHT is one of that predictor's key components, alongside the Branch Target Buffer (BTB) and Return Address Stack (RAS). [citation: IF unit and predictor context]

Within that dynamic predictor:

  • The BHT predicts branch direction, taken or not taken.
  • The BTB records target PC addresses for branch instructions to speed determination of taken-branch addresses.
  • The RAS stores return addresses for decoded function calls, so a popped return address can be used as the predicted next PC for a function return. [citation: dynamic predictor components]

Verification relevance

The BHT can be a target of functional coverage in processor verification. In the cited UVM-based verification work, a coverpoint named "Write to every line of BHT array" is associated with 256 bins, because the evaluated BHT has 256 entries. Each bin counts writes issued to a particular BHT entry. [citation: BHT coverage and size]

This verification setup treats such coverpoints as fully covered when each bin is hit at least 100 times, in the context of the described simulation-based verification framework. [citation: coverage completion criterion]

Scope note

The 256-entry size is an implementation detail of the processor design discussed in the cited verification work, not a universal property of all Branch History Tables. [citation: BHT implementation-specific size]

LINKED ENTITIES

2 links
Instruction Fetch Unit PART_OF
branch predictor PART_OF

CITATIONS

6 sources
6 citations
[1] BHT purpose and indexing [PDF] UVM-based verification of RISC-V superscalar processors
[2] IF unit and predictor context [PDF] UVM-based verification of RISC-V superscalar processors
[3] dynamic predictor components [PDF] UVM-based verification of RISC-V superscalar processors
[4] BHT coverage and size [PDF] UVM-based verification of RISC-V superscalar processors
[5] coverage completion criterion [PDF] UVM-based verification of RISC-V superscalar processors
[6] BHT implementation-specific size [PDF] UVM-based verification of RISC-V superscalar processors