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Bare-Metal Execution

Concept WIKI v2 · 7/10/2026

Bare-metal execution is a mode in which verification software runs directly on a silicon prototype without an operating system, debuggers, device drivers, or other system software. It is commonly used in post-silicon validation during early bring-up, when prototypes are unstable and cannot yet boot an OS. This execution mode imposes unique constraints on tools—including limited observability, the absence of I/O services, the need for on-platform self-sufficiency, and reliance on lightweight checking methods such as multi-pass consistency checking—and is used by tools such as Threadmill and supported by instruction-accurate simulators like ExactStep.

Bare-Metal Execution

Definition and Context

In post-silicon hardware validation, bare-metal execution describes a mode in which verification software runs directly on the silicon prototype without the support of an operating system, debuggers, device drivers, or other system software [1]. Because early silicon prototypes are typically unstable and lack a complete software stack, bare-metal execution is often the only option available to bring-up engineers, and tools intended to run in this mode must be deployed "in the very early stages of the post-silicon validation effort when the OS cannot yet be run on the system" [2].

A tool that operates in this mode is called a bare-metal exerciser. Threadmill, developed at IBM Research – Haifa, is one such tool [2].

Characteristics

Bare-metal execution environments used for post-silicon validation exhibit several defining characteristics:

  • No operating system services — file systems, device drivers, and standard I/O facilities are unavailable [3].
  • No debugging infrastructure — interactive debuggers and on-platform observability mechanisms are typically absent or extremely limited [1].
  • Limited memory and state — some platforms (e.g., on-wafer testers) provide very limited memory for programs and data [3].
  • High overhead for memory and state operations — loading and offloading memory and state information is expensive because no OS services can mediate the transfers [3].
  • Real-time execution speed — once running, bare-metal code executes at full silicon speed without OS-induced jitter [3].

Design Implications for Tools

The constraints of bare-metal execution drive several design decisions for any tool that must run in this mode:

  1. Simplicity — Because hardware failures are hard to debug without observability tools, the exerciser itself must be simple software [2].
  2. On-platform self-sufficiency — A bare-metal exerciser, once loaded on silicon, generates, executes, and checks tests "indefinitely" without further interaction with the environment [4].
  3. Lightweight generation engine — Because silicon time is expensive, the on-platform test generation engine must be fast and light, in contrast to more sophisticated pre-silicon generators [2].
  4. Pre-computed payloads — Heavy computations such as floating-point operand generation are performed off-platform; only their results are embedded in the exerciser image [3].
  5. Minimal interaction with environment — The tool should avoid operations such as reading files from I/O devices, which are not supported in bare-metal mode [2].
  6. Lightweight checking — Reference models and complex checking machinery are less appealing because off-platform usage requires costly result offloading and on-line usage consumes precious execution cycles [2].

Checking Strategies Under Bare-Metal Constraints

Because traditional reference models are impractical, bare-metal exercisers typically rely on lightweight checking methods:

  • Multi-pass consistency checking — Each test-case is executed multiple times and the end-of-test values of selected system resources (memory, registers) are compared for consistency [2].
  • Injected and natural variability — The effectiveness of consistency checking depends on existing or injected differences between passes, such as variations in thread scheduling or system operation modes [2].
  • User-specified self-checking procedures — Verification engineers may supply procedures that verify predictable aspects of an abstract scenario [2].

Host-Side Execution of Bare-Metal Images

Instruction-accurate instruction set simulators also commonly run bare-metal executables compiled for a target ISA, providing a host-side environment with no operating system on the emulated target. ExactStep, for example, supports RISC-V (RV32IMAC, RV64IMAC), MIPS (mips-i), and ARM-v6m targets and "is used to run bare-metal executables compiled for those ISAs" [5]. ExactStep executes one instruction per call to cpu::step(), prioritizing ease of extension for cosimulation, peripheral development, and SystemC bus interfacing over raw execution performance [5].

Related Concepts

For more detail on a concrete realization of a bare-metal exerciser, see the article on Threadmill, the tool used in the verification of the IBM POWER7 processor [1]. For an instruction-accurate simulator that runs bare-metal images on a host, see ExactStep [5].

LINKED ENTITIES

1 links

CITATIONS

7 sources
7 citations
[1] Bare-metal execution means running verification software directly on a silicon prototype without an operating system, debuggers, device drivers, or other system software. Threadmill: A Post-Silicon Exerciser for Multi-Threaded Processors
[2] Bare-metal tools must be deployed in the very early stages of post-silicon validation when the OS cannot yet run on the system and operations such as reading files from an I/O device are not supported. Threadmill: a post-silicon exerciser for multi-threaded processors
[3] Bare-metal systems have no OS services, offer real-time execution speed but low dynamic observability, and have high overhead for loading and offloading memory and state information; some platforms (e.g., on-wafer) provide very limited memory for programs and data. Threadmill: a post-silicon exerciser for multi-threaded processors
[4] A bare-metal exerciser, once loaded on silicon, will generate, execute, and check tests indefinitely without further interaction with the environment. Threadmill: a post-silicon exerciser for multi-threaded processors
[5] The on-platform test generation engine must be fast and light compared to pre-silicon verification technologies, and checking must rely on simple methods such as multi-pass consistency checking and user-specified self-checking procedures. Threadmill: a post-silicon exerciser for multi-threaded processors
[6] Heavy generation tasks such as floating-point operand generation are performed off-platform; their results are embedded as pre-computed operand-sets in the exerciser image. Threadmill: a post-silicon exerciser for multi-threaded processors
[7] ExactStep is an instruction-accurate instruction set simulator that is used to run bare-metal executables compiled for supported ISAs (RISC-V, MIPS, ARM-v6m). ultraembedded/exactstep

VERSION HISTORY

v2 · 7/10/2026 · minimax/minimax-m3 (current)
v1 · 7/9/2026 · minimax/minimax-m3