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B-Extension

Concept WIKI v1 · 6/14/2026

The B-Extension is a RISC-V instruction set extension designed to accelerate bit manipulation instructions. Its goals are to reduce code size, improve performance, lower power consumption, and speed up bit-manipulation workloads, making it relevant for embedded applications using RISC-V 64-bit processors.

Overview

The B-Extension is an extension to the RISC-V instruction set architecture (ISA). It is developed to provide hardware acceleration for bit manipulation instructions, targeting embedded and high-performance computing workloads such as IoT, edge computing, and high-performance embedded processors [1].

Design Goals

According to the surveyed literature, the B-Extension is designed to:

  • Reduce code size for bit-manipulation-heavy programs.
  • Improve performance by accelerating bit-manipulation instructions directly in hardware.
  • Reduce power consumption for embedded workloads.
  • Provide acceleration of bit manipulation instructions on RISC-V 64-bit processors used in embedded and high-performance applications [1].

Verification of B-Extension Implementations

Verifying a RISC-V processor that supports the B-Extension requires additional test infrastructure beyond standard RISC-V test suites, because the base riscv-tests suite alone does not comprehensively cover B-Extension instructions. The survey identifies the following verification approach for a 64-bit high-performance embedded processor supporting the B-Extension (Meng et al., 2022):

  1. Dynamic simulation is used to functionally verify B-Extension behavior at the RTL level.
  2. RISC-V instruction self-checking test set and imperas-riscv tests are used to supplement riscv-tests and provide additional coverage of the B-Extension [1].
  3. FPGA prototyping is employed to test the stability and correctness of processor operation under realistic conditions [1].
  4. Performance is measured using Dhrystone, CoreMark, and Comprehensive Analysis benchmarks to assess the impact of the B-Extension [1].

Related Concepts

  • FPGA Prototyping: A verification technique used to evaluate and validate implementations of the B-Extension on real hardware before silicon fabrication.

References

  • Meng Z, Zhang Y, Zhou J, Guo Z (2022) Design of 64-Bit High-Performance Embedded Processor Supporting RISC-V B-Extension. 2022 IEEE 16th International Conference on Anti-counterfeiting, Security, and Identification (ASID), Xiamen, China. 28–32. doi:10.1109/ASID56930.2022.9995771.

LINKED ENTITIES

1 links
FPGA Prototyping EVALUATES

CITATIONS

6 sources
6 citations
[1] The B-Extension is developed to reduce code size, improve performance, reduce power consumption, and realize the acceleration of bit manipulation instructions. Survey of Verification of RISC-V Processors - Springer Nature
[2] Verification of a RISC-V processor supporting the B-Extension uses dynamic simulation and FPGA prototype verification. Survey of Verification of RISC-V Processors - Springer Nature
[3] RISC-V instruction self-checking test set and imperas-riscv tests supplement riscv-tests to cover the B-Extension. Survey of Verification of RISC-V Processors - Springer Nature
[4] FPGA prototyping is used to test the stability and correctness of B-Extension processor operation. Survey of Verification of RISC-V Processors - Springer Nature
[5] Performance of the B-Extension processor is measured using Dhrystone, CoreMark, and Comprehensive Analysis tests. Survey of Verification of RISC-V Processors - Springer Nature
[6] The B-Extension is used in 64-bit high-performance embedded RISC-V processors for IoT, edge, and high-performance computing applications. Survey of Verification of RISC-V Processors - Springer Nature