B-Extension

Concept

The B-Extension is a RISC-V instruction set extension designed to accelerate bit manipulation instructions. Its goals are to reduce code size, improve performance, lower power consumption, and speed up bit-manipulation workloads, making it relevant for embedded applications using RISC-V 64-bit processors.

First seen 6/14/2026

Last seen 6/14/2026

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Overview

The B-Extension is an extension to the RISC-V instruction set architecture (ISA). It is developed to provide hardware acceleration for bit manipulation instructions, targeting embedded and high-performance computing workloads such as IoT, edge computing, and high-performance embedded processors ^[1].

Design Goals

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FPGA Prototyping ← evaluates 91% 1e

FPGA prototyping is used to verify the RISC-V B-extension processor.

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CITATIONS

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[1] The B-Extension is developed to reduce code size, improve performance, reduce power consumption, and realize the acceleration of bit manipulation instructions. Survey of Verification of RISC-V Processors - Springer Nature

[2] Verification of a RISC-V processor supporting the B-Extension uses dynamic simulation and FPGA prototype verification. Survey of Verification of RISC-V Processors - Springer Nature

[3] RISC-V instruction self-checking test set and imperas-riscv tests supplement riscv-tests to cover the B-Extension. Survey of Verification of RISC-V Processors - Springer Nature

[4] FPGA prototyping is used to test the stability and correctness of B-Extension processor operation. Survey of Verification of RISC-V Processors - Springer Nature

[5] Performance of the B-Extension processor is measured using Dhrystone, CoreMark, and Comprehensive Analysis tests. Survey of Verification of RISC-V Processors - Springer Nature

[6] The B-Extension is used in 64-bit high-performance embedded RISC-V processors for IoT, edge, and high-performance computing applications. Survey of Verification of RISC-V Processors - Springer Nature