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Axe Memory Consistency Checker

Concept WIKI v1 · 5/27/2026

Axe is referenced as an example of a verification approach that checks execution traces against higher-level memory-model semantics, rather than only checking trace equivalence. In the TestRIG context, Axe is cited as relevant to future memory-concurrency testing for RISC-V CPUs using RVFI-DII instruction streams.

Overview

The Axe Memory Consistency Checker is cited in the TestRIG paper as an example of a tool or approach for checking execution behavior against higher-level memory-model semantics. The paper contrasts this kind of checking with verification engines that test traces only for equivalence.

Role in memory-concurrency testing

The cited TestRIG work identifies memory concurrency testing as a future direction. It proposes that TestRIG should support memory-model testing by injecting RVFI-DII instruction streams with specified timestamps into multiple shared-memory cores, enabling precise stimulation of concurrency behaviors.

In that setting, the paper says a more advanced verification engine would be needed: one that tests RVFI traces not only for equivalence, but also against higher-level memory-model semantics, "as in Axe [9]." This positions Axe as a reference point for memory-model-aware trace checking.

Relationship to TestRIG

TestRIG is described as an open-source repository of TestRIG-compatible implementations and verification engines, intended to accelerate processor development and move toward a standardized RISC-V testing framework. Axe is not described as part of the current TestRIG implementation in the provided evidence; rather, it is cited as an example for the kind of memory-model semantic checking that future TestRIG memory-concurrency support would require.

Key technical points

  • Axe is associated with checking higher-level memory-model semantics.
  • The TestRIG paper distinguishes this semantic checking from simple RVFI trace equivalence checking.
  • TestRIG memory-concurrency testing is proposed to use timestamped RVFI-DII instruction streams across multiple shared-memory cores.
  • Axe is cited as an example relevant to that proposed memory-model testing capability.

LINKED ENTITIES

2 links
RVFI-DII related_input_trace_interface
RISC-V applied_context

CITATIONS

5 sources
5 citations
[1] TestRIG future work proposes support for memory-model testing and memory concurrency testing. Randomized Testing of RISC-V CPUs using Direct
[2] The proposed TestRIG concurrency tests would inject RVFI-DII instruction streams with specified timestamps into multiple shared-memory cores to stimulate concurrency behaviors. Randomized Testing of RISC-V CPUs using Direct
[3] The TestRIG paper says this concurrency-testing direction would require a verification engine that checks RVFI traces not only for equivalence but also against higher-level memory-model semantics, as in Axe. Randomized Testing of RISC-V CPUs using Direct
[4] QCVEngine is described as the initial TestRIG verification engine, while the memory-model testing direction would require a more advanced verification engine. Randomized Testing of RISC-V CPUs using Direct
[5] The TestRIG paper says current TestRIG-compatible implementations and verification engines were collated into an open-source TestRIG repository, and frames TestRIG as a path toward a standardized RISC-V testing framework. Randomized Testing of RISC-V CPUs using Direct