Axe Memory Consistency Checker
ConceptAxe is referenced as an example of a verification approach that checks execution traces against higher-level memory-model semantics, rather than only checking trace equivalence. In the TestRIG context, Axe is cited as relevant to future memory-concurrency testing for RISC-V CPUs using RVFI-DII instruction streams.
First seen 5/27/2026
Last seen 5/27/2026
Evidence 1 chunks
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WIKI
Overview
The Axe Memory Consistency Checker is cited in the TestRIG paper as an example of a tool or approach for checking execution behavior against higher-level memory-model semantics. The paper contrasts this kind of checking with verification engines that test traces only for equivalence.
Role in memory-concurrency testing
NEIGHBORHOOD
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2 linksRVFI-DII related_input_trace_interface The evidence states that RVFI-DII instruction streams with specified timestamps would be injected into multiple shared-memory cores for memory-model testing, and that traces would need to be checked against higher-level memory-model semantics as in Axe.
RISC-V applied_context The evidence places the proposed TestRIG memory-model testing work in the context of a standardized testing framework for RISC-V.
CITATIONS
5 sources5 citations — click to expand
[1] TestRIG future work proposes support for memory-model testing and memory concurrency testing. Randomized Testing of RISC-V CPUs using Direct
[2] The proposed TestRIG concurrency tests would inject RVFI-DII instruction streams with specified timestamps into multiple shared-memory cores to stimulate concurrency behaviors. Randomized Testing of RISC-V CPUs using Direct
[3] The TestRIG paper says this concurrency-testing direction would require a verification engine that checks RVFI traces not only for equivalence but also against higher-level memory-model semantics, as in Axe. Randomized Testing of RISC-V CPUs using Direct
[4] QCVEngine is described as the initial TestRIG verification engine, while the memory-model testing direction would require a more advanced verification engine. Randomized Testing of RISC-V CPUs using Direct
[5] The TestRIG paper says current TestRIG-compatible implementations and verification engines were collated into an open-source TestRIG repository, and frames TestRIG as a path toward a standardized RISC-V testing framework. Randomized Testing of RISC-V CPUs using Direct