Assertion-Based Verification

Assertion-Based Verification (ABV) is a hardware functional-verification methodology that uses assertions—formal statements of expected design behavior—to specify and automatically check design properties. Recent work describes ABV as a key approach for verifying modern hardware designs because of its efficiency and effectiveness.

Assertions and automation

In practice, ABV work often focuses on SystemVerilog Assertions (SVAs). Manually writing high-quality SVAs remains labor-intensive and error-prone, which has motivated research into automated and assisted assertion generation.

A recent review surveys automatic assertion miners, comparing widely adopted techniques, their methodologies, and their limitations.

LLM-based assertion generation

Recent work has also explored LLM-based assertion synthesis. For example, AssertCoder generates SVAs directly from multimodal hardware design specifications such as text, tables, diagrams, and formulas. It uses modality-sensitive preprocessing and semantic analyzers to extract structured representations aligned with signal-level semantics, then drives assertion synthesis with multi-step chain-of-thought prompting. It also uses mutation-based evaluation with model checking to assess and refine the generated assertions.

Use in hardware fuzzing

ABV is integrated into hardware fuzzing workflows as a validation technique. In this context, assertions encode expected hardware properties inside the DUT, and assertion violations can indicate potential vulnerabilities.