ASSERT_KNOWN Assertion

Overview

ASSERT_KNOWN is an assertion macro used in OpenTitan's SystemVerilog hardware design (RTL) to check that an IP block's outputs are always driven to well-defined logic values (not X or Z) during simulation. It is one of the standard immediate or concurrent assertion idioms adopted across OpenTitan hardware IP.

Purpose

The ASSERT_KNOWN assertion exists to catch design issues such as:

• Uninitialized flops or signals that propagate X values during simulation.
• Outputs that are inadvertently left undriven (high-impedance) when they should always carry a defined value.
• Incorrect default or reset values that allow unknown values to leak to downstream blocks.

By catching these problems early in simulation, ASSERT_KNOWN improves debuggability and reduces the risk of silicon surprises caused by unknown-propagation issues.

Usage Requirement (D1 Signoff Checklist)

According to the OpenTitan Signoff Checklist, one of the design-stage (D0 → D1) requirements is:

All the outputs of the IP have ASSERT_KNOWN assertions.

In other words, every output port of an IP block must be guarded by an ASSERT_KNOWN check that fires (or logs an error) whenever the signal carries an unknown value in simulation. This requirement helps ensure that:

• The unit does not inadvertently propagate X values through downstream interfaces.
• The block does not break top-level functionality by leaving outputs in unknown states at the boundary.

Relation to D1 Preconditions

The D1 checklist also requires that the unit be able to be instantiated and connected at the top level RTL, and that it must not break top-level functionality — for example, propagating X through TileLink-UL interfaces, continuously asserting alerts or interrupts, or creating undesired TileLink-UL transactions. Adding ASSERT_KNOWN on every output directly supports this requirement by giving verification engineers a clear signal when an output is not properly driven.

Where It Fits

ASSERT_KNOWN is part of the broader set of RTL design checks used in OpenTitan hardware IPs. It is typically applied in the unit-level SystemVerilog (.sv) file alongside other assertions that cover interface protocols, FIFO pointers, FSM state encoding, and security-relevant behavior.

See Also

• RTL — the Register-Transfer Level design domain in which ASSERT_KNOWN is used.
• OpenTitan Signoff Checklist — the source-of-truth for when ASSERT_KNOWN coverage is required.
• Development Stages — the D0 → D1 → D2 → … lifecycle during which this assertion requirement is enforced.