ASSERT_KNOWN Assertion
ConceptASSERT_KNOWN is a SystemVerilog assertion used in OpenTitan hardware IP design to verify that all outputs of an IP block are driven to known (non-X, non-Z) values. Including these assertions on every output is a required checklist item for transitioning from development stage D0 to D1.
First seen 7/16/2026
Last seen 7/16/2026
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ASSERT_KNOWN Assertion
Overview
ASSERT_KNOWN is an assertion macro used in OpenTitan's SystemVerilog hardware design (RTL) to check that an IP block's outputs are always driven to well-defined logic values (not X or Z) during simulation. It is one of the standard immediate or concurrent assertion idioms adopted across OpenTitan hardware IP.
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1 connectionsASSERT_KNOWN assertions are required on all outputs of the IP as part of RTL requirements.
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[1] All the outputs of the IP have ASSERT_KNOWN assertions is a D0-to-D1 signoff checklist requirement. Signoff Checklist - OpenTitan Documentation
[2] ASSERT_KNOWN helps prevent the unit from propagating X through TileLink-UL interfaces and other top-level interfaces, which is required for D1 signoff. Signoff Checklist - OpenTitan Documentation