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Addressing Modes

Concept WIKI v1 · 7/8/2026

In computer architecture, an addressing mode specifies how the operand of a machine instruction is located in memory or in registers. Addressing modes are a key design choice in both RISC and CISC instruction sets, and complex variants appear in architectures such as PowerPC and x86. The set of modes supported by an ISA affects code size, performance, and the cost of generating memory accesses in tools such as test generators.

Addressing Modes

Definition

An addressing mode is the mechanism an instruction set architecture (ISA) uses to compute the location of an operand referenced by a machine instruction. Different addressing modes trade off generality, instruction length, and the number of memory references required to reach an operand.

Role in ISA design

Addressing modes are a defining feature of instruction set design and are commonly discussed in comparisons between architectural families:

  • CISC architectures historically provided a rich set of addressing modes, allowing a single instruction to specify operands using complex combinations of registers, displacements, and indirect references.
  • RISC architectures traditionally favor a small, regular set of simple addressing modes, with more complex address calculations performed by separate instructions.

The set of modes supported directly affects code size and execution performance, since modes that can reach more memory locations with fewer instructions reduce both the static instruction count and the dynamic overhead of multi-instruction address sequences [arxiv:1101.5364].

Near addressing and code size

When a program's working set exceeds the range addressable by a single short displacement, compilers must emit additional instructions (for example, loading a base address into a register) before the actual memory access. Architectures that provide "near" addressing modes can reach such operands directly, yielding significant code size reductions and performance improvements. This issue arises concretely in embedded and real-time control code, which tends to use large numbers of global variables whose addresses lie outside the range reachable from a global pointer [arxiv:2605.25602].

Complex addressing modes in test generation

Because real ISAs expose many addressing modes, tools that synthesize memory accesses — such as model-based test program generators — must reason about the constraints those modes impose. Generic constraint-satisfaction algorithms can model new addressing modes modularly, allowing the same engine to handle complex addressing modes across multiple architectures including PowerPC and x86 [Lewin et al., 2002].

See also

LINKED ENTITIES

2 links
Memory Access Generation USES
Complex Addressing Modes PART_OF

CITATIONS

3 sources
3 citations
[1] Complex addressing modes in PowerPC and x86 are handled by a generic constraint-satisfaction algorithm for memory access generation. Constraint satisfaction for test program generation
[2] Addressing modes are a distinguishing characteristic compared between RISC and CISC architectures and affect code size and performance. RISC and CISC
[3] Near addressing modes allow operands (e.g., global variables in real-time control code) outside the range of short displacements to be reached directly, reducing code size and improving performance. Code size reduction by advanced near addressing modes