Overview

Rocket is identified in the MorFuzz USENIX Security 2023 paper as one of three real-world open-source processors used to evaluate a RISC-V prototype of MorFuzz, alongside CVA6 and BOOM. The evaluated processors are described collectively as covering microarchitectures ranging from simple in-order cores to complex out-of-order superscalar cores. [citation: rocket-morfuzz-evaluation]

Role in MorFuzz evaluation

MorFuzz was implemented as a prototype for the RISC-V architecture and evaluated on Rocket as a device under test. The study reports that, across its evaluation, MorFuzz achieved up to 4.4× more state coverage than DifuzzRTL and up to 1.6× more state coverage than riscv-dv. It also reported reaching DifuzzRTL's 24-hour coverage in about 30 minutes and riscv-dv's 24-hour coverage in about 2.4 hours. [citation: morfuzz-evaluation-results]

Co-simulation consideration: delayed write-back

Rocket is specifically used as an example of a processor that supports delayed write-back. The MorFuzz paper notes that, for Rocket, write-back data for long-latency instructions such as multiply, divide, and floating-point instructions may not be ready at the commit stage. This motivated MorFuzz's compatible co-simulation design, which separates state comparison into a commitment stage and a judgment stage to accommodate microarchitectural differences between processors. [citation: rocket-delayed-writeback]

Related entities

• MorFuzz: evaluates Rocket as one of its RISC-V processor targets. [citation: rocket-morfuzz-evaluation]