Overview

SystemVerilog assertions are described in the evidence as the usual way to express ISA-specified behavior for formal verification of processor submodules. In that flow, formal verification exhaustively explores input combinations against the specified behavior, helping find submodule bugs before system-level integration or late software bring-up. [C1]

Role in processor verification

In the cited RISC-V microarchitecture verification context, SystemVerilog assertions support a hybrid verification strategy. Formal verification is valuable for checking submodules, while simulation remains necessary for validating large integrated processors, SoC integration, and software execution on the device under test. [C1]

The evidence also notes that processor verification is not made complete by any single method. Coverage reports from simulation can show what has been exercised, but processor complexity, instruction sequences, pipeline events, and custom RISC-V extensions require broader validation strategies. [C2]

Relationship to formal verification

Formal verification uses SystemVerilog assertions to encode behavior that should match ISA expectations. This makes SystemVerilog assertions part of the specification-checking mechanism in the referenced processor verification approach. [C1]

Limitations and surrounding workflow

The evidence does not claim that SystemVerilog assertions alone guarantee defect-free hardware. Instead, it frames formal verification as one part of a larger verification flow that also includes simulation, reference-model comparison, hardware-assisted validation, and operational software testing. [C1][C2]