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RISC-V Formal Verification Framework

Tool WIKI v1 · 5/30/2026

RISC-V Formal Verification Framework is the SymbioticEDA/riscv-formal GitHub project, described publicly as a RISC-V formal verification framework. It is a Verilog repository and is cited in cross-level RISC-V processor-verification literature as a formal, model-checking-based approach, with such approaches noted as potentially facing scalability issues.

Overview

RISC-V Formal Verification Framework refers to the SymbioticEDA/riscv-formal project, whose public GitHub listing describes it as a "RISC-V Formal Verification Framework." The repository is listed as a Verilog project and, in the provided public context, has 631 stars and 104 forks, with the latest recorded update at 2026-05-15T10:52:06Z. [identity]

Role in RISC-V verification literature

The framework is cited in the DATE 2022 paper Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging as reference [19], named "RISC-V formal verification framework" and pointing to https://github.com/SymbioticEDA/riscv-formal. [paper-reference]

In the same paper, the authors discuss available RISC-V verification resources, including directed test suites and "a few formal approaches" based on model checking techniques. The RISC-V Formal Verification Framework is one of the cited formal approaches in that context. [model-checking]

Notes and limitations

The DATE 2022 discussion notes that formal, model-checking-based techniques can be "possibly susceptible to scalability issues." This statement is made about the cited class of formal approaches rather than as a repository-specific benchmark result. [scalability]

Repository metadata

  • Repository: SymbioticEDA/riscv-formal
  • Public description: "RISC-V Formal Verification Framework"
  • Primary language listed: Verilog
  • Public-context activity metrics: 631 stars, 104 forks
  • Public-context update timestamp: 2026-05-15T10:52:06Z [identity]

LINKED ENTITIES

2 links
Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging MENTIONS
Model Checking IMPLEMENTS

CITATIONS

4 sources
4 citations
[1] identity SymbioticEDA/riscv-formal
[2] paper-reference Cross-Level Processor Verification via
[3] model-checking Cross-Level Processor Verification via
[4] scalability Cross-Level Processor Verification via