Overview

RISC-DV is a random instruction generator used in RISC-V CPU verification. In the Ibex verification flow described in the evidence, the UVM-based testbench runs binaries built from source produced by the RISC-DV random instruction generator.

Role in Ibex verification

In the Ibex flow, RISC-DV-generated source is built into test binaries that the UVM testbench loads and executes on the Ibex core. The testbench stimulates Ibex to execute the program stored in memory, then compares the core trace log against a golden instruction-set simulator trace from Spike. The same environment also collects coverage information about executed instructions and operands, and uses test and coverage plans to track verification completeness.

The evidence describes additional Ibex verification stimulus beyond the instruction stream itself, including randomized memory timings, memory errors, interrupts, and debug requests. A co-simulation system can run Spike in lockstep with the Ibex core and compare executed instructions and memory transactions against the ISS behavior.

Relationship to Core-V-Verif

The available evidence also describes Core-V-Verif as a RISC-V functional verification environment that supports generated test programs. Its UVM environment can use a random instruction generator to create test programs, and generated programs may be self-checking or not self-checking depending on the test type. The provided excerpt's overview figure references riscv-dv in the Core-V-Verif flow, but the surrounding text does not provide implementation details for RISC-DV itself.

Evidence limitations

The provided evidence establishes RISC-DV's role as a random instruction generator in verification flows, especially for Ibex. It does not establish details such as RISC-DV's maintainers, license, command-line interface, supported ISA extensions, repository location, or internal generator architecture.