RISC-DV
ToolRISC-DV is identified in the available evidence as a RISC-V random instruction generator used in open-source RISC-V core verification flows, notably to produce source for binaries executed by the Ibex UVM testbench.
First seen 5/27/2026
Last seen 5/28/2026
Evidence 3 chunks
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Overview
RISC-DV is a random instruction generator used in RISC-V CPU verification. In the Ibex verification flow described in the evidence, the UVM-based testbench runs binaries built from source produced by the RISC-DV random instruction generator.
Role in Ibex verification
NEIGHBORHOOD
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4 sources4 citations — click to collapse
[1] RISC-DV is used as a random instruction generator whose source output is built into binaries run by the Ibex UVM verification testbench. [PDF] UVM based design verification of a RISC-V CPU core - POLITesi
[2] The Ibex testbench stimulates the core to execute a program stored in memory, compares the core trace log against a Spike ISS trace, and collects instruction and operand coverage. [PDF] UVM based design verification of a RISC-V CPU core - POLITesi
[3] The Ibex verification environment adds randomized memory timings, memory errors, interrupts, and debug requests, and can use lockstep co-simulation with Spike. [PDF] UVM based design verification of a RISC-V CPU core - POLITesi
[4] Core-V-Verif supports generated test programs and can use a random instruction generator to create them; the overview figure references riscv-dv in the verification flow. [PDF] UVM based design verification of a RISC-V CPU core - POLITesi